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1 Scalable Pattern Matching for High Speed Networks Authors: Christopher R.Clark and David E. Schemmel Publisher: Proceedings of IEEE Symposium on Field- Programmable Custom Computing Machines(FCCM) Present: Kia-Tso Chang Date: November 1 2007
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Three designed method on FPGA 1. brute-force, 2. deterministic finite automata (DFA) 3. non-deterministic finite automata (NFA).
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Distributed comparators and Character Decoder 3
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Pattern-matching module using multi-character decoder 4
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Four-character parallel NFA circuit for the pattern “abcde” 5
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Upper bound of per matcher
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Each FPGA logic element (LE) can implement up to a four-input logic gate and a flip-flop,
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Upper bound of per matcher
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Experiment result 10
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Experiment result 11
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Throughput and capacity trade- off summary 12
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Throughput and capacity trade- off summary
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Performance comparison with previous work
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