1. Pipelined Architecture For Multi-String Match Department of Computer Science and Information Engineering National Cheng Kung University, Taiwan R.O.C. Authors: Derek Pao, Wei Lin, and Bin Liu Publisher: IEEE Computer Architecture Letters, 30 May 2008. IEEE computer Society Digital Library. IEEE Computer Society Present: Chia-Ming,Chuang Date: 10, 8, 2008 1

2. Outline 1. Introduction 2. Pipelined Architecture 3. Performance evaluation 4. Conclusion 2

3. Introduction (1/6) A string Y of length n is a sequence of characters c 1 c 2 ……c n. Let Σ = {Y 1, Y 2,...Y N } be a finite set of strings called keywords or signatures proposed hardware solutions are based on the well-known Aho-Corasick (AC) algorithm, where the system is modeled as a deterministic finite automaton(DFA) we present a pipelined processing approach to the implementation of AC algorithm, called P- AC. 3

4. Introduction (2/6) CLOCKCURRENTINPUTNEXT STATEedge 1ROOTaaforward edge 2apapforward edge 3appappforward edge 4appaNULLcross edge 5paspasforward edge 6pastpastforward edge 7past Transition rule table Input data:.appastxyz 4

5. Introduction (3/6) Forward edges cross edges 5

6. Introduction (4/6) 6

7. Introduction (6/6) 7

8. Introduction (5/5) 8

9. Outline 1. Introduction 2. Pipelined Architecture 3. Performance evaluation 4. Conclusion 9

10. Pipelined Architecture (1/6) 10

11. Pipelined Architecture (2/6) Assume the pipeline has k+1 stages numbered from 0 to k last stage is only used to buffer the search result of stage (k-1). longer than k characters are divided into segments of length k last segment whose length can be less than k 11

12. Pipelined Architecture (3/6) local transition tables (LT) can be implemented using hardware hashing For long strings with more than k characters, the match-result will be generated by the aggregation unit (AU). transition rule table (T D ) to determine the next state segment ID will be passed to the corresponding partial match unit (PM i ) of the AU. (PM i ) sends a lookup request to the conditional match table (CMT); 12

13. Pipelined Architecture (4/6) andTestInstructions instrument and Test Instructionsinstrument andTestInstructionsrument andionsInst ructrume Test Boolean flag L is equal to 1 if the segment is part of a long string 13

14. Pipelined Architecture (5/6) 14

15. Pipelined Architecture (6/6) 15

16. Outline 1. Introduction 2. Pipelined Architecture 3. Performance evaluation 4. Conclusion 16

17. Performance evaluation (1/2) There are k+3 memories in the system (k memories for the pipeline unit) 2 memories for the DFA units and 1 memory for the CMT). DFA unit requires 2 memories because there are 2 types of edges (Forward edges or cross edges) 17

18. Performance evaluation (2/2) 18

19. Outline 1. Introduction 2. Pipelined Architecture 3. Performance evaluation 4. Conclusion 19

20. Conclusion (1/1) if 2-port memories are available, we can implement 2 pipelines on the same device that share the lookup tables. The system throughput can be doubled with little overhead. Using the Xilinx Virtex-5 FPGA that operates at 550 MHz, the throughput of P-AC is up to 8.8 Gbps. 20