1. Ring Counter
Discussion 11.3
Example 32

2. 4-Bit Ring Counter

3. Note non-blocking assignment
module ring4(
input wire clk,
input wire clr,
output reg [3:0] q );
// 4-bit Ring Counter
clk or posedge clr)
begin
if(clr == 1)
q <= 1;
else
q[3] <= q[0];
q[2:0] <= q[3:1];
end
endmodule
Note non-blocking assignment

4. Aldec Active-HDL Simulation

5. Johnson Counter

6. johnson4.v module johnson4( input wire clk, input wire clr,
output reg [3:0] q );
// 4-bit Johnson Counter
clk or posedge clr)
begin
if(clr == 1)
q <= 0;
else
q[3] <= ~q[0];
q[2:0] <= q[3:1];
end
endmodule

7. Johnson Counter

8. A Random Number Generator

9. q3 q2 q1 q0 C E F B
q3 q2 q1 q0 A D

10. rand4.v module rand4( input wire clk, input wire clr,
output reg [3:0] q );
// 4-bit Random number generator
clk or posedge clr)
begin
if(clr == 1)
q <= 1;
else
q[3] <= q[3] ^ q[0];
q[2:0] <= q[3:1];
end
endmodule

11. A Random Number Generator

12. Clock Pulse
clk
inp Q2 Q0 Q1
outp

13. clk_pulse.v ); module clk_pulse( input wire clk; input wire clr;
input wire inp;
output wire outp; );
reg [2:0] Q;
// clock pulse generator
clk or posedge clr)
begin
if(clr == 1)
Q <= 0;
else
Q[2] <= inp;
Q[1:0] <= Q[2:1];
end
assign outp = Q[2] & Q[1] & ~Q[0];
endmodule
clk_pulse.v

14. clk
inp Q2 Q0 Q1
outp