1. Kazi Fall 2006 EEGN 4941 EEGN-494 HDL Design Principles for VLSI/FPGAs Khurram Kazi Some of the slides were taken from K Gaj’s lecture slides from GMU’s VHDL course webpage

2. 2Kazi Fall 2006 EEGN 494 Signal Generator using Finite State Machine Method

3. 3Kazi Fall 2006 EEGN 494 Signal Generator using Finite State Machine Method library ieee; use ieee.std_logic_1164.all; ENTITY signal_gen1 IS PORT ( clk:IN STD_LOGIC; reset:IN STD_LOGIC; wave: OUT STD_LOGIC); END signal_gen1; Architecture finite_state_machine OF signal_gen1 IS TYPE states IS (zero, one, two, three, four, five, six, seven); signal Wstate,: states; signal temp : STD_LOGIC; BEGIN PROCESS (clk, reset) IF (reset = '0') then Wstate <= zero; ELSIF (clk'EVENT and clk = '1') THEN CASE Wstate IS WHEN zero => temp <= '0'; Wstate <= one; WHEN one => temp <= '1'; Wstate <= two; WHEN two => temp <= '0'; Wstate <= three; WHEN three => temp <= '1'; Wstate <= four; WHEN four => temp <= '1'; Wstate <= five; WHEN five => temp <= '1'; Wstate <= six; WHEN six => temp <= '0'; Wstate <= seven; WHEN seven => temp <= '0'; Wstate <= zero; END CASE; END PROCESS; END finite_state_machine;

4. 4Kazi Fall 2006 EEGN 494 Clock divider

5. 5Kazi Fall 2006 EEGN 494 Assignment: Clock divider Design a clock divider that can divides the original clock by 2, 4, 8, 16 and 32 Run the simulations to ensure that all the divided frequencies are working properly. Write the report that includes the code and how did you verify that the appropriate frequencies were generated properly Due Date November 2

6. 6Kazi Fall 2006 EEGN 494 Basic FIFO (First In First Out) FIFO used for rate adaptation Buffering temporarily Normally has two different clocks FIFO full FIFO empty FIFO almost full FIFO almost empty Can be RAM based or Flip flop based

7. 7Kazi Fall 2006 EEGN 494 Basic FIFO Write pointer Data in Read pointer Data out

8. 8Kazi Fall 2006 EEGN 494 Inputs and Outputs of the FIFO Inputs reset, clk, datain (7:0), wr_rd (when ‘1’, write otherwise read) Outputs dataout (7:0) (FIFO status signals) FIFO Empty (fifo_empty) FIFO Full (fifo_full) FIFO almost Empty (fifo_almost_full) FIFO almost Full (fifo_almost_empty)

9. 9Kazi Fall 2006 EEGN 494 Building Blocks of the FIFO Write Pointer -- Counter Read Pointer -- Counter Data Storage element -- Memory or Flipflops Status --Combinatorial logic

10. 10Kazi Fall 2006 EEGN 494 Definitions of FIFO Status signals Status FIFO Empty (condition when all the data within the FIFO has been read and no new data is stored in the FIFO) FIFO Full (all the memory locations in the FIFO have been written to) FIFO almost full (certain threshold of memory locations of the FIFO have been written to) FIFO almost empty (Only certain memory locations of the FIFO can be read from as there is no more new data written into the FIFO)

11. 11Kazi Fall 2006 EEGN 494 Assignment: FIFO design Design a 256 byte wide FIFO Develop the testbench that writes data to the FIFO, reads data from the FIFO, generates FIFO almost full, FIFO full, FIFO almost empty, FIFO empty conditions Write a report that includes, the description of how the FIFO works, vhdl code, critical simulation waveform results Due Date November 9. Note of caution: if you have not designed the FIFO by November 2, most likely you will not be able to finish the assignment since the verification will take much longer.