1. UCSD VLSI CAD Laboratory BACUS-2008 Revisiting the Layout Decomposition Problem for Double Patterning Lithography Andrew B. Kahng, Chul-Hong Park, Xu Xu, Hailong Yao http://vlsicad.ucsd.edu/ University of California, San Diego

2. UCSD VLSI CAD Laboratory BACUS-2008 Outline  Background  Contributions  DPL Layout Decomposition Flow  DPL Color Assignment Problem Formulation  Experimental Results  Summary

3. UCSD VLSI CAD Laboratory BACUS-2008 Background: DPL  DPL is a primary lithography candidate for 32nm node  Partitions dense circuit patterns into two separate exposures  Improves resolution and depth of focus (DOF)  Two primary approaches  LELE (litho-etch-litho-etch)  Self-aligned  Major concern is overlay control  Requires more accurate overlay metrology, more representative sampling, reduced model residuals, and improved overlay correction  ITRS DPL overlay control requirement is 6-9nm  challenging for production deployment

4. UCSD VLSI CAD Laboratory BACUS-2008 Background: Layout Decomposition  Two features are assigned opposite colors if their spacing is less than the minimum coloring spacing  IF two features within minimum coloring spacing cannot be assigned different colors  THEN at least one feature is split into two or more parts  Pattern split increases manufacturing cost, complexity  Line ends  corner rounding  Overlay error and interference mismatch  line edge errors  tight overlay control  Optimization : minimize cost of layout decomposition

5. UCSD VLSI CAD Laboratory BACUS-2008 Outline  Background  Contributions  DPL Layout Decomposition Flow  DPL Color Assignment Problem Formulation  Experimental Results  Summary

6. UCSD VLSI CAD Laboratory BACUS-2008 Contributions  Reference [1] (our group, Proc. ICCAD-2008)  Integer linear programming (ILP)  Conflict cycle detection and removal  Report unresolvable conflict cycles  This work  Consider all feasible splitting points for layout features  Different ILP formulation  minimize design changes, line-ends; maximize overlap length  Phase conflict detection (PCD) method [2]  good solution quality, much less runtime  Node-deletion bipartization (NDB) method [3]  also fast, worse solution quality  Report deleted conflict edges  more direct metric of design changes [1] A. B. Kahng, C.-H. Park, X. Xu and H. Yao, “Layout Decomposition for Double Patterning Lithography”, Proc. IEEE Intl. Conf. on Computer-Aided Design, 2008. [2] C. Chiang, A. B. Kahng, S. Sinha, X. Xu, and A. Zelikovsky, "Fast and Efficient Bright-Field AAPSM Conflict Detection and Correction", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 26(1) (2007), pp. 115-126. [3] A. B. Kahng, S. Vaya and A. Zelikovsky, "New graph bipartizations for double-exposure, bright fieldalternating phase-shift mask layout", Proc. Asia and South Pacific Design Automation Conference, 2001, pp. 133-138.

7. UCSD VLSI CAD Laboratory BACUS-2008 Outline  Background  Contributions  DPL Layout Decomposition Flow  DPL Color Assignment Problem Formulation  Experimental Results  Summary

8. UCSD VLSI CAD Laboratory BACUS-2008 DPL Layout Decomposition Flow  Layout fracturing  Polygons  rectangles  Conflict graph construction  Projection computation  Adjacent nodes connected with conflict edges  Node splitting and graph updating  Split at all feasible dividing points  Update the conflict graph  Compute overlap lengths  For each pair of touch rectangles, based on projections  Color assignment  ILP, PCD or NDB based graph bipartization and color assignment Graph construction Node splitting and graph updating ILP/PCD/NDB based color assignment Layout fracturing Projection computation Compute overlap lengths

9. UCSD VLSI CAD Laboratory BACUS-2008 Example: DPL Layout Decomposition  Polygonal layout features  rectangles  Conflict graph construction  Compute projections and feasible dividing points  Node splitting and graph updating  ILP, PCD, or NDB method obtains final coloring solution (a) (b) (c) (d) e1e1 e2e2

10. UCSD VLSI CAD Laboratory BACUS-2008 Outline  Background  Contributions  DPL Layout Decomposition Flow  DPL Color Assignment Problem Formulation  Experimental Results  Summary

11. UCSD VLSI CAD Laboratory BACUS-2008 Min-Cost Color Assignment Problem  Given: A list of rectangles R which is color assignable, and maximum distance between two features, t, at which the color assignment is constrained  Find: color assignment of rectangles to minimize the total cost  Subject to:  For any two adjacent non-touching rectangles with 0<d(i,j)≤ t, assign different colors  For any two touching rectangles (i.e., d(i,j) = 0), if they are assigned different colors, there is a corresponding cost c ij where, d(i,j) = distance between features of i and j t = minimum color spacing between features of i and j

12. UCSD VLSI CAD Laboratory BACUS-2008 Fracturing and Conflict Graph Construction  Given a layout, a rectangular layout is obtained by fracturing polygons into rectangles  Minimum-sliver fracturing [1]  Easier feature operations  Avoids design rule violation  Given a rectangular layout, construct the conflict graph G =(V, E C  E T )  Node n represents a feature  Conflict edge e c i,j : non-touching features n i and n j within distance t  Touching edge e t i,j : touching features n i and n j horizontal vertical min-sliver n1n1 n2n2 n3n3 n4n4 n5n5 n6n6 e c 1,3 e c 3,5 e c 5,6 e t 1,2 e t 2,3 e t 3,4 e t 4,5 [1] A. B. Kahng, X. Xu and A. Zelikovsky, “Fast Yield-Driven Fracture for Variable Shaped-Beam Mask Writing", Proc. SPIE Conf. on Photomask and Next-Generation Lithography Mask Technology, 2006, pp. 62832R-1 - 62832R-9.

13. UCSD VLSI CAD Laboratory BACUS-2008 Node Splitting and Graph Updating  Split all nodes with feasible dividing points  Update conflict graph  Conflict graph may not be two-colorable after node splitting  Two cases (1)Overlap length less than overlap margin (2)No dividing point with nonzero overlap length  Minimized conflict edges are deleted  Design change: preferentially between features of different cell instances  ILP/PCD/NDB based method for graph bipartization nknk njnj dividing point o p,q nini nlnl o q,p npnp nqnq d < t nknk njnj no dividing point nini nlnl d < t Case (1) Case (2)

14. UCSD VLSI CAD Laboratory BACUS-2008 Method 1: ILP Based Min-Cost Color Assignment  x i : binary variable (0/1) for the color of rectangle r i  y ij : binary variable for touching edge e t ij  E T  y ij = 0 when x i = x j  y ij = 1 when x i  x j  z ij : binary variable for conflict edge e c ij  E C  z ij = 0 when x i  x j  z ij = 1 when x i = x j  Minimize:  Subject to: l ij : length of rectangle edge of r i opposite to the touching edge between r i and r j FS min : minimum feature size L ij : overlap length between touching rectangles r i and r j OM: required overlap margin

15. UCSD VLSI CAD Laboratory BACUS-2008 Method 2: Phase Conflict Detection Based Graph Coloring  Gadget based approach: optimal edge- deletion bipartization for planar graph [1]  Two main steps  Heuristic planar graph embedding  Optimal conflict removal for planar graph  Conflict graph  conflict cycle graph  Conflict (green) edge  feature (red) edge  Touching (blue) edge  conflict (black) edge  Edge cost  Conflict edge:   design change  Touching edge  cut and overlap length   /2: design rule or OL violation   +  /OL ij : no design rule or OL violation  Output: deleted edges with two-colorable graph e1e1 e2e2 conflict edge feature edge conflict edge e1e1 e2e2 Conflict graph touching edge Conflict cycle graph [1] C. Chiang, A. B. Kahng, S. Sinha, X. Xu, and A. Zelikovsky, "Fast and Efficient Bright-Field AAPSM Conflict Detection and Correction", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 26(1) (2007), pp. 115-126.

16. UCSD VLSI CAD Laboratory BACUS-2008 Method 3: Node-Deletion Bipartization Based Graph Coloring  Node-deletion graph bipartization [1]  Conflict cycle graph construction  Conflict (green) edge  new node, feature (red) and conflict (black) edge  Touching (blue) edge  new node and two feature (red) edges  Only newly inserted nodes are deletable  Cost of new nodes: same as in PCD  Output: deleted nodes  Map back to conflict and touching edges  After PCD or NDB step, color with breadth first search (BFS) based process touching edge e1e1 e2e2 conflict edge new node n1n1 n2n2 conflict edge feature edge Conflict graph Conflict cycle graph [1] A. B. Kahng, S. Vaya, A. Zelikovsky, "New Graph Bipartizations for Double-Exposure, Bright Field Alternating Phase-Shift Mask Layout", Proc. Asia and South Pacific Design Automation Conference, 2001, pp. 133-138.

17. UCSD VLSI CAD Laboratory BACUS-2008 Layout Partitioning  Conflict graph is sparse: due to poly-to-cell boundary and whitespace  Many islands found in the conflict graph  Layout partitioning  Partitions conflict graph into connected components  Each component has separate conflict graph  No edges or nodes of a polygon occur in multiple components  Color each component separately  Final solution: union of solutions for all components  Improves runtime and memory efficiency

18. UCSD VLSI CAD Laboratory BACUS-2008 Outline  Background  Contributions  DPL Layout Decomposition Flow  DPL Color Assignment Problem Formulation  Experimental Results  Summary

19. UCSD VLSI CAD Laboratory BACUS-2008 Testcases Design#Cells#Polygons#Rectangles Min. SpacingMin. Width Before x 0.4 Scaling Before x 0.4 Scaling AES17304903943623801405610040 TOP-B6080054500020668001405610040 TOP-C3050002725000103340001405610040 TOP-D121600109000041336001405610040  AES: real-world design  Top-B, Top-C, Top-D  Artificial designs  >600 types of cell masters  Artisan 90nm libraries  Placement: 70% and 90% utilization  Minimum design rule: GDS scaled down by 0.4x  Minimum spacing:140nm  56nm  Minimum width: 100nm  40nm

20. UCSD VLSI CAD Laboratory BACUS-2008 ILP Results  Sweep t and placement utilization  Various metrics: deleted conflict edges, overlap length and number of cuts  Minimum overlap length  overlap margin 8nm  No design rule violation

21. UCSD VLSI CAD Laboratory BACUS-2008 PCD Results  Sweep t and placement utilization  Various metrics: deleted conflict edges, overlap length and number of cuts  Minimum overlap length  overlap margin 8nm  No design rule violation

22. UCSD VLSI CAD Laboratory BACUS-2008 NDB Results  Sweep t and placement utilization  Various metrics: deleted conflict edges, overlap length and number of cuts  Minimum overlap length  overlap margin 8nm  No design rule violation

23. UCSD VLSI CAD Laboratory BACUS-2008 Comparison (1)  Higher priority on deleted edges  design changes  Deleted edges: ILP < PCD < NDB  Same deleted edges: ILP obtains minimal cuts with maximal overlap length

24. UCSD VLSI CAD Laboratory BACUS-2008 Comparison (2)  Same deleted edges: ILP obtains larger mean overlap length  Solution quality: ILP > PCD > NDB  Runtime: ILP > NDB > PCD

25. UCSD VLSI CAD Laboratory BACUS-2008 Outline  Background  Contributions  DPL Layout Decomposition Flow  DPL Color Assignment Problem Formulation  Experimental Results  Summary

26. UCSD VLSI CAD Laboratory BACUS-2008 Summary  Three approaches: ILP, PCD and NDB methods  Address DPL layout decomposition at 45nm and below  Improve overlap length and lithography yield  Experimental results are promising  Overlap lengths  overlap margin  Report all necessary design changes  Ongoing work  Optimal timing/power model guardbanding under bimodal CD distribution in DPL  Variability-aware DPL layout decomposition cost function  Minimize difference between pitch distributions of two masks  Minimize number of distinct DPL layout solutions across all instances of same master cell  Balanced mask layout density  Integration of forbidden pitch intervals

27. UCSD VLSI CAD Laboratory BACUS-2008