1. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Topics n Memory elements. n Basics of sequential machines.

2. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Memory elements n Stores a value as controlled by clock. n May have load signal, etc. n In CMOS, memory is created by: –capacitance (dynamic); –feedback (static).

3. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Variations in memory elements n Form of required clock signal. n How behavior of data input around clock affects the stored value. n When the stored value is presented to the output. n Whether there is ever a combinational path from input to output.

4. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Memory element terminology n Latch: transparent when internal memory is being set from input. n Flip-flop: not transparent - reading input and changing output are separate events.

5. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Clock terminology n Clock edge: rising or falling transition. n Duty cycle: fraction of clock period for which clock is active (e.g., for active-low clock, fraction of time clock is 0).

6. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Memory element parameters n Setup time: time before clock during which data input must be stable. n Hold time: time after clock event for which data input must remain stable. clock data

7. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Dynamic latch Stores charge on inverter gate capacitance:

8. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Latch characteristics n Uses complementary transmission gate to ensure that storage node is always strongly driven. n Latch is transparent when transmission gate is closed. n Storage capacitance comes primarily from inverter gate capacitance.

9. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Latch operation  = 0: transmission gate is off, inverter output is determined by storage node.  = 1: transmission gate is on, inverter output follows D input. n Setup and hold times determined by transmission gate - must ensure that value stored on transmission gate is solid.

10. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Stored charge leakage n Stored charge leaks away due to reverse- bias leakage current. n Stored value is good for about 1 ms. n Value must be rewritten to be valid. n If not loaded every cycle, must ensure that latch is loaded often enough to keep data valid.

11. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Stick diagram  V DD V SS D Q

12. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Layout DQ V DD V SS 

13. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Multiplexer dynamic latch

14. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Non-dynamic latches n Must use feedback to restore value. n Some latches are static on one phase (pseudo-static) - load on one phase, activate feedback on other phase.

15. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Recirculating latch Static on one phase:

16. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Clocked inverter symbol circuit

17. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Clocked inverter operation  = 0: both clocked transistors are off, output is floating.  = 1: both clocked inverters are on, acts as an inverter to drive output.

18. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Clocked inverter latch

19. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Clocked inverter latch operation  = 0: i1 is off, i2-i3 form feedback circuit.  = 1: i2 is off, breaking feedback; i1 is on, driving i3 and output. Latch is transparent when  = 1.

20. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Flip-flops n Not transparent - use multiple storage elements to isolate output from input. n Major varieties: –master-slave; –edge-triggered.

21. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Master-slave flip-flop  DQ masterslave

22. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Master-slave operation  = 0: master latch is disabled; slave latch is enabled, but master latch output is stable, so output does not change.  = 1: master latch is enabled, loading value from input; slave latch is disabled, maintaining old output value.

23. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Sequential machines n Use memory elements to make primary output values depend on state + primary inputs. n Varieties: –Mealy - outputs function of present state, inputs; –Moore - outputs depend only on state.

24. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Sequential machine definition n Machine computes next state N, primary outputs O from current state S, primary inputs I. n Next-state function: –N =  (I,S). n Output function (Mealy): –O = (I,S).

25. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR FSM structure

26. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Constraints on structure n No combinational cycles. n All components must have bounded delay.

27. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR

28. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR

29. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Clock skew Clock must arrive at all memory elements in time to load data.