1. BWRC 2003 Winter Retreat Jan M. Rabaey EECS Dept. Univ. of California, Berkeley

2. BWRC 2003 Winter Retreat Meso-scale low-cost radio’s for ubiquitous wireless data acquisition that are fully integrated –Size smaller than 1 cm 3 minimize power/energy dissipation – Limiting power dissipation to 100  W enables energy scavenging and form self-configuring ad-hoc networks containing 100’s to 1000’s of nodes Meso-scale low-cost radio’s for ubiquitous wireless data acquisition that are fully integrated –Size smaller than 1 cm 3 minimize power/energy dissipation – Limiting power dissipation to 100  W enables energy scavenging and form self-configuring ad-hoc networks containing 100’s to 1000’s of nodes PicoRadio’s ─ The Mission Ubiquitous Sensor and Monitor Networks

3. BWRC 2003 Winter Retreat Wireless Sensor Networks Dominant trend in Wireless Industry: More Bits/sec/(Hz) Wireless sensor networks offer interesting alternative: More bits/$/nJ Infrastructure maintenance Traffic management Medical Energy management Smart buildings

4. BWRC 2003 Winter Retreat PicoRadio Team Faculty –Jan Rabaey –Paul Wright –Kannan Ramchandran –Ali Niknejad –Alberto Sangiovanni-Vincentelli Testbed –Fred Burghardt –Sue Mellers –Jonathan Reason –Hugo Shi –Reto Stutz RF –Yuen Hu Chee –Richard Lu –Brian Otis –Nathan Pletcher –Uli Schuster Energy Scavening and Packaging –Mike Montero –Dan Odell –Shad Roundy Design Tools –Marco Sgroi –Rong Zhong Networking, MAC and Locationing –Chunlong Guo –Tufan Karalar –Enyi Lin –Nir Matalon –Dragan Petrovic –Rahul Shah –Jana Van Greunen –Mei Xu –Charlie Zhong Digital Network Processor –Josie Ammer –Mika Kuulusa –SuetFei Li –Jacob Poppe –Huifang Qin –Mike Sheets –Jonathan Tsao –Ruth Wang –Janie Zhou

5. BWRC 2003 Winter Retreat PN-IIIv1: The First Self-Contained Sensor Node Components and battery mounted on back 5 cm 7.6 mm 3 cm Solar Cell (0.5 mm) Battery (3.6 mm) PCB (1 mm) Chip encapsulation (1.5 mm) Version 1: Light Powered Version 2: Vibration Powered Size determined by power dissipation (< 0.5 mW avg)

6. BWRC 2003 Winter Retreat Voltage Supply Voltage Supply 20MHz Clock Source Voltage Supply OOK Receiver Flash Storage Sensor2 Sensor1 PrgThresh0PrgThresh1 OOK Transmitter Tx0Tx2 User Interface SIF = sensor interface LocalHW MAC DW8051 256 DATA sfrbus or membus? ADC 4kB XDATA 16kB CODE PHY Chip Supervisor SIF ADC Serial GPIO FlashIF Serial Digital Network Processor (“Charm”) RF Transceiver (“Strange”) Solar Cell PN-IIIv1 Architecture: The “Quark” ChipSet Microresonators (“Up and Down”) Powertrain

7. BWRC 2003 Winter Retreat “SmorgasBoard” Prototyping All Components of PNv3 FBAR based radio Solar-cell based energy scavenging Dynamic Memory Power-down Test Vibration-based energy scavenging

8. BWRC 2003 Winter Retreat “Strange”: Back to The Future (Courtesy of Brian Otis) D. Yee, UCB © 2000 - Direct Conversion f c = 2GHz >10000 active devices no off-chip components © 1949 - superregenerative fc= 500MHz 2 active devices high quality off-chip passives - hand tuning

9. BWRC 2003 Winter Retreat Back to The Future Matching Network MOD1 MOD2 OSC1 OSC2 Preamp PA Simplicity Rules Minimizes use of active components Uses simple modulation scheme (OOK) Allows efficient non-linear PA Down-conversion through non-linearity (Envelope Detector) Tx and Rx in 3-4 mW range (when on) FBAR-based RF Filter A f clock RF Filter Env Det  f clock RF Filter Env Det 

10. BWRC 2003 Winter Retreat The “Strange” Components OSC/PA PA LNA OSC ENV Test Inductors 2mm 300  m Testchip in 0.13  m CMOS Fully functional CoCo LxLx CxCx RxRx Agilent FBAR Technology

11. BWRC 2003 Winter Retreat An Operational PicoRadio (RF) !!! 2mm 300  m Built by chaining prototype-chip components using chip-on-board assembly. Implements complete TX and RX functionality FBAR

12. BWRC 2003 Winter Retreat An Operational PicoRadio (RF) 2mm 300  m Out In RF Built by chaining prototype-chip components using chip-on-board assembly. Implements complete TX and RX functionality FBAR

13. BWRC 2003 Winter Retreat “Strange”─The Integrated Version Receiver RF Amp Test LNA Test Diff Osc PA Test TX1 TX2 Env Det Test Passive Test Structures In fab as of December 10 Technology: 0.13  m CMOS combined with off-chip FBARs Carrier frequency: 1.9 GHz 0 dBm OOK Two Channels Channel Spacing ~ 50MHz 10-160 kbps/channel Technology: 0.13  m CMOS combined with off-chip FBARs Carrier frequency: 1.9 GHz 0 dBm OOK Two Channels Channel Spacing ~ 50MHz 10-160 kbps/channel 4 mm

14. BWRC 2003 Winter Retreat Pro’s or Con’s of Simple Radio’s Small Change in Path Loss Has Dramatic Impact on Transmission Quality –Channel is either “good” or “bad” Reducing Symbol Time (or Increasing Data Rate) Reduces Energy/bit for same QOS –Factor 2 reduction in symbol time for 1.5 db in path gain Go for fastest possible radio that simple scheme allows (limited by ISI) Go for fastest possible radio that simple scheme allows (limited by ISI) Simulated response of PN3v1 radio

15. BWRC 2003 Winter Retreat Integrated NanoMechanical Filter Technology (In cooperation with R. Howe and BSAC) Substrate riri roro g Drive Electrode RBAR: Radial Bulk Annular Resonator Sense Electrode B. Bircumshaw and A. Pisano

16. BWRC 2003 Winter Retreat Integrated NanoMechanical Filter Technology Shear Ring Resonator (SRR) Differential drive and differential sense electrodes are alternated along the circumference: + 24 dB in Dynamic Range (S. Bhave and R. Howe) –Drive +Drive –Sense+Sense SiC versions of RBAR and SRR in fab

17. BWRC 2003 Winter Retreat LocalHW MAC DW8051 256 DATA Interconnect network ADC 4kB XDATA 16kB CODE PHY Chip Supervisor SIF ADC Serial GPIO FlashIF Serial Reactive Digital Network Processor (“charm”) Reactive inter- and intra-chip signaling Aggressive Use of Power-Domains Chip Supervisor Manages Activity DLL (MAC) App/UI Network Transport Baseband RF (TX/RX) Sensor/actuator interface Locationing Aggregation/ forwarding User interface Sensor/ actuators Antenna Chip Supervisor Reactive radio Energy train Prototyped on FPGA In Fab March 03 1 mW on < 10  W sleep Size: 6 mm 2

18. BWRC 2003 Winter Retreat Synchronization Block Diagram Synch Algorithm: 1.Carrier Detect Indicates carrier detected to DLL layer Sets threshold for timing estimation 2.Symbol and Packet Timing Estimation Sets timing and threshold for bit decisions 3.Bit Decisions Envelope Detector Analog Filter ADC Carrier Sense ? Slicer Matched Filter Symbol and Packet Timing Estimation Carrier Detected Est. Threshold TimingThreshold Bits Estimated Complexity: 65 kGates

19. BWRC 2003 Winter Retreat Locationing Engine ─ Floor plan and Dataflow Performs first-order locationing based on hop-count

20. BWRC 2003 Winter Retreat Prototyping Protocol Processor on FPGA Commercial Vertex Board Total: 150 kGates (not including memory) FITS EASILY ON SINGLE VERTEX Total estimated area: 3.5 mm 2

21. BWRC 2003 Winter Retreat NMOS 0.75V/-0.25V PMOS 0.25V/-0.5V * M6 power loss * M9M9 M8M8 M7M7 CL K CL K_ Power Domains─ State-Preserving Power-Down Switched-Capacitor Converter for Standby Supply Voltage Generation 1V => 200mV 1.3uA => 6.5uA Output Power = 1.3uw V out = 190mv +/- 3mv Efficiency: 90% w/o clock power 80% w/ clock power 1.3 mm 2 SRAM Leakage Control Test Chip (0.13um Process, with 4K bytes SRAM embedded )

22. BWRC 2003 Winter Retreat Power Domains State-Preserving Power-Down Ramped Supply Memory Data Bit 4 @ Address 0xFFh 300mV Standby Vdd 1 V Standard Vdd 1V Measured leakage current Of 4 KB SRAM Factor 12 Some interesting observations : measured retention voltage: 250 mV (100 mV simulated) leakage power reduction larger than anticipated: 5.4  W at 0.3 V versus 241  W at 1V (factor 45)

23. BWRC 2003 Winter Retreat Verifying the Overall System― Emulating a PicoRadio Network BEE (Berkeley Emulation Engine) –An Hierarchical Mesh-Connected Array of 20 Xilinx Vertex-2000 FPGA’s –High-level Mapping Software Support – Simulink/Stateflow as the Preferred Input Format –Extensive Debugging/Monitoring Support Easily Supports 16+ PicoNodes and Evolved Channel Models A New and Exciting Trend in System Verification Xbar FPGA Inter-board connectors 96 bit inter-Xbar buses

24. BWRC 2003 Winter Retreat The Bottom Line: Total PicoNode Power Dominated by channel monitoring power Dominated by TX (+RX) power Increasing data rate of radio reduces total power dissipation of PicoNode! (based on real traffic models and implementation parameters) Parameters: 3 packets/sec 200 bits/packet 20 bit pre-amble 5 neighbors Synchronization using serendipitous rendez- vous (or cycled receiver) with Ton/T = 0.1 Pave = 250  W

25. BWRC 2003 Winter Retreat The Impact of The Wake-Up Radio Factor 5 to 10 reduction over cycled receiver

26. BWRC 2003 Winter Retreat Why an FPGA Implementation First? Sensor networks (even when statically deployed) are very dynamic – Susceptible to rapid changes in the channel. This is especially the case when using simple radio ’ s (with limited diversity) –In low-data rate applications, anything learned about the channel is irrelevant when the next packet arrives (coherence time is less than 1 sec) Solutions: –Make data-link layer reliable –Use diversity (time, frequency, space) ─ Only spatial diversity offered by redundancy in sensor networks meets the cost and energy requirements as well as the constraints offered by ad-hoc networks. Bottom Lines: – Extensive statistics gathering at all the levels of the stack an absolute necessity – Given these observations, committing to a fixed protocol stack is premature Some Important Lessons Learned

27. BWRC 2003 Winter Retreat Lessons Learned: Extensive Statistics Gathering a Necessity Recorder Manager SMS Packet Drivers Session Counters CRC Counters Counter Control Service SW HW SW Media Access Controller Transmit Controller & Datapath Receive Controller & Datapath Datalink Layer Neighbor List Service Energy-Aware Routing Algorithm Location Service Network Layer SW HW Application Packet Drivers Temp. Sensor HW Light Sensor Humidity Sensor Accel- erometer HW SW Mag- netometer Monitor HW SW Sensor Board I Sensor Board II Queuing Service SW Physical Layer Bluetooth Radio Environment User Interface Programs Application Layer Statistics and Management Service parameter configuration Added “statistics and management server” to PicoNodeI Protocol stack

28. BWRC 2003 Winter Retreat Measurements: Link Reliability (narrow band Bluetooth channel) 79% 13% 5% 2%1%0% % total returned packets Lesson Learned: With 2 bits of ECC, we can recover approximately 18% more data packets. Or …

29. BWRC 2003 Winter Retreat Extend correlator from 4 to 10 taps 4 tap 10 tap

30. BWRC 2003 Winter Retreat The Variability of Link Quality Broadcast quality over time as measured at the BWRC round-table on a Friday PicoRadio Meeting NAMP Meeting

31. BWRC 2003 Winter Retreat The Impact of Spatial Diversity Adding a single node already changes broadcast reliability dramatically – spacial diversity is the preferred way to provide robustness in sensor networks Deep fade due to multipath 2 nodes 3 nodes Data gathered using PicoNodeI testbed

32. BWRC 2003 Winter Retreat Making The Data Link More Reliable Use only links that prove to be reliable over the long term Use RTS/CTS scheme before transmission to perform instantaneous “channel estimation” Revised link layer keeps track of reliability of channel

33. BWRC 2003 Winter Retreat Energy Scavenging - Solar Wires to load 3 cm Regulator and battery 0 0.5 1 1.5 2 2.5 050100150200 minutes volts Battery charging from solar cells Lamp 12 inches from cells Load disconnected

34. BWRC 2003 Winter Retreat Energy Scavenging - Vibration Vibrometer Piezo Generator Super Capacitor Simulated Load Power circuit 100  A load 1 mA load

35. BWRC 2003 Winter Retreat Energy Scavenging - Vibration Piezo-bender prototyped for “in-tire” sensor network

36. BWRC 2003 Winter Retreat Status/Summary PicoNodes becoming a reality! PicoNodes becoming a reality! PicoNode IIIv1 First integrated sub-mW node, combining custom components with some of the shelf elements – Average Power dissipation estimated around 400  W Operation of FBAR radio demonstrated; Integration version (2 channel) in fab Full functionality of protocol processor demonstrated on FPGA – system level verification under progress; processor chip in fab in March Concepts of power-domains and voltage-down retention demonstrated Energy scavenging sub-system implemented and functionality demonstrated

37. BWRC 2003 Winter Retreat Perspectives: Beyond PN III Extending the Lifetime of Sensor Networks Wake-up Radio Localization Design Methodology (with GSRC) –“Ambient Intelligence one of main GSRC drivers” Bringing Power even Lower! –Reliable computation on unreliable platforms Computation in the ultra low-voltage space Exploring New Application Spaces

38. BWRC 2003 Winter Retreat Lifetime of Sensor Networks How to mitigate hot-spots in sensor networks? Intelligent routing Data aggregation Distributed coding Topology planning Altruistic nodes Dynamic relocation of functionality The hot-spot problem D. Petrovic, R. Shah, K. Ramchandran Project funded by NSF Established strict upper-bounds on lifetime!

39. BWRC 2003 Winter Retreat Combining Aggregation and Coding Controller Sensors Border Node 4 Unique ID Payload 20 32 42 213 Ordering corresponds to integer 2 = payload of packet 4 1 Coding by Ordering Store information in data order Packet aggregation suppresses header overhead

40. BWRC 2003 Winter Retreat Computation in the Ultra-Low Voltage Space Power dissipation becoming the main roadblock towards further integration! –Intel Processor Integration is “power constrained” –Drain-source leakage a major fraction of power dissipation – direct function of supply voltage –Gate leakage one of the main emerging challenges – again, a very strong function of supply voltage Aggressive voltage scaling seems to be the only plausible answer Offers the opportunity for reducing power dissipation of mobile sensor nodes by other major fraction Minimum Feature Size (micron) 10 1 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Supply Voltage (V) SIA Roadmap not aggressive enough?

41. BWRC 2003 Winter Retreat Computation in the Ultra-Low Voltage Space How low can we go? Gain limitations but lower bound on supply voltage on a couple of kT/q While many noise sources scale, some do not! –Thermal noise –Soft errors Circuits are bound to start producing errors when supply voltages are aggressively scaled! Variability of threshold voltage remains approximately constant, causing gate performance to vary widely  Explore circuit and architecture techniques that deal with performance variations (e.g., self-timed) and are (somewhat) resilient to errors!

42. BWRC 2003 Winter Retreat Some First-Order Results Studied distribution of delay over wide range of process parameters (simple inverter chain) using Monte Carlo Analysis PDF shows lognormal distribution – this is, Gaussian is not a good model

43. BWRC 2003 Winter Retreat Some Intriguing New Applications Everyday Computing Addressing the “everyday problem” (e.g. Where are my keys?) Courtesy of Mik Lamming and Jim Rowson, HP Labs

44. BWRC 2003 Winter Retreat ISSCC 2002 Jack Raper Award for Outstanding Technology Directions Paper “PicoRadios for Wireless Sensor Networks: The Next Challenge in Ultra-Low Power Design” J. M. Rabaey, J. Ammer, T. Karalar, S. Li, B. Otis, M. Sheets, T. Tuan