1. Multiprocessors II Andreas Klappenecker CPSC321 Computer Architecture

2. The AMD Opteron (Topic suggested by Paul Krizak)

3. Main features 64 bit processor backwards compatible HyperTransport Double Data Rate (DDR) memory controller

4. The Opteron Architecture

5. Caches 64 Kbytes L1 data cache two-way set associative 64 Kbytes L1 instruction cache two-way set associative L2 cache for both instruction and data 16-way set associative data cache protected by ECC if a cache line contains an instruction, then ECC bits store predecode and branch prediction information

6. HyperTransport Each processor has three data links two for communication between processors one for I/O Data rate is 3.2 Gbytes/s each direction Consequence: SMP capability

7. HyperTransport

8. Two Processor Server

9. Four Processor Server