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Area-performance tradeoffs in sub-threshold SRAM designs
George Cramer Ping-Chen Huang
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Motivation Consumer applications require low power and small memory design Implementing SRAM in subthreshold needs read/write assist circuits to maintain stability Area trades off with stability and power
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Project Outlines Investigate the area-performance trade-offs of 3 subthreshold SRAM designs Four metrics: stability, delay, power, area Fixed stability as the only constraint Determine the most area-efficient subthreshold SRAM design as Vdd scales down
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Subthreshold SRAM designs
N. Verma and A. P. Chandrakasan, “A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy,” IEEE Journal of Solid-State Circuits, vol. 43, no. 1, Jan. 2008, pp B. H. Calhoun and A. P. Chandrakasan, "A 256-kb 65-nm sub-threshold SRAM design for ultra-low-voltage operation," IEEE Journal of Solid-State Circuits, vol. 42, no. 3, Mar. 2007, pp
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Modeling of SRAM Stability
(a) Hold stress (b) Read stress (c) Write stress VQ low: M2 is off VQ low: M2 is off VQ low: M1 is off VQ high: M2 is off VQ high: M3 is off VQ high: VQB = 0
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Modeling of SRAM Delay Hold margin case:
-> SNMhold = *VDD Read margin case: Write margin case:
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Noise Margin Modeling Results
Desired Read Margin = 80mV Desired Write Margin = 150mV
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Modeling of Delay and Power
EOP Assume α=1
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SRAM Performance 6T design has smallest read delay for its smallest equivalent resistance from internal node to bitline 10T design has smallest EOP
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Area-EOP Trade-off
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