1. 4-bit ALU Yamei Li, Yuping Liang Hua Qu, James Hsu
Advisor: Dave Parent
12/6/2005

2. Agenda Introduction Project (Experimental) Details Summary
ALU
Adder
DFF
MUX
Summary
Project result
Lesson learned
Acknowledgement

3. Introduction
The 4-bit ALU that our group designed can perform the following functions:
Adder, NOR, OR, and AND.
The 4-bit ALU operates at 200 MHz and use 5.8mW of Power and occupied an area of mm x 280mm.
The 4-bit ALU is made up of 4 identical 1-bit ALU, and 14 DFFs.

4. Project Description and ALU schematic
The 4-bit ALU is broken down into sub blocks consisting of:
4 1-bit Adders
4 4to1 MUXs
4 AND, 4 NOR and 4 OR gate
10 input DFFs and 4 output DFFs

5. Longest Path Calculations
Note: All widths are in microns
and capacitances in fF

6. 4-bit ALU Layout and LVS

7. ALU Simulations and Power test

8. DFF schematic & LVS report

9. DFF layout

10. DFF Hold Time Fall& Rise

11. DFF Setup Time Rise & Fall

12. 1 Bit Adder Schematic,Layout & LVS

13. 1 Bit Adder Post Simulation

14. 4 Bit Adder Schematic and Simulation

15. MUX schematics

16. MUX layout and LVS Size of 4 MUX = 5% of ALU area
Size of one MUX = 28mm x 70mm
Size of 4 MUX = 5% of ALU area

17. MUX Simulation Before Extraction
Simulation results before extraction
TPHL= ns , TPLH=1.045 ns
Propagation delay < 4 LL x 0.294ns=1.177ns

18. MUX Post Simulation Results from Post Extraction Simulation
TPHL=0.758 ns , TPLH=0.755 ns
27% faster

19. Summary
After this project, we became familiar with Cadence tool and the fundamental concepts of IC design.
Our project has 338 transistors and 18 terminals.
The total area is =280mm x 600mm
The power is=3.4W/cm2
Lessons learned
how to fix the LVS error
Learn how to work in a team
Learn how to make trade offs

20. Acknowledgements
Thanks to Professor D. Parent guidance and unlimited patience.
Thanks to Cadence Design Systems for the VLSI lab