1. Copyright  1999 Daniel D. Gajski IP – Based Design Methodology Daniel D. Gajski University of California gajski@uci.edu http://www.ics.uci.edu/~gajski

2. Copyright  1999 Daniel D. Gajski Outline Drivers of IP business Obstacles to IP success Possible solutions Business models Future

3. Copyright  1999 Daniel D. Gajski IP Drivers Product complexity Market pressure Expertise shortage Productivity gap Business model

4. Copyright  1999 Daniel D. Gajski Solving Complexity / Productivity Problems 1. IP 2. 3. 4. IP

5. Copyright  1999 Daniel D. Gajski Obstacles to IP Success Partially abstracted design process Simulation based design flow –Simulation models are not easily synthesizable IP definition (parameterization, verification, characterization) IP-centric models for SOC –No separation of computation and communication –Need for encapsulation Reuse automation –IP do not fit into past methodologies and tools IP-centric methodology No clearly defined business models –Volume, value-added and protection

6. Copyright  1999 Daniel D. Gajski Solving Complexity / Productivity Problems Higher level of abstraction –Specification –Architecture –Communications –Components (IP) –Tools and methodologies Standardization –Languages –Models –Protocols –Documentation (IP)

7. Copyright  1999 Daniel D. Gajski Simulation Based Design Flow Finite State Machine 3.415 2.715 case X is when X1 => when X2 => Table Lookup ControllerMemory Simulatable but not synthesizable

8. Copyright  1999 Daniel D. Gajski Quality, Verifiability, Testability, Characterizability No. of parameters, Generality 1 single instance IP Definition Quality, verification, characterization vs. parameterization

9. Copyright  1999 Daniel D. Gajski FSMFSMD S1S1 S3S3 S2S2 Count  0 Count = 0 S1S1 S3S3 S2S2 Count  0 Count = 0 x = 0 y = 0... x = 0 y = 1... x = 1 y = 0... count = n temp1 = a(i) + b(i) temp2 = c(i) + d(i) count = count - 1 s(i) = temp1 * temp2 RTL Specs

10. Copyright  1999 Daniel D. Gajski RFMemRF ControllerProcessor (controller & datapath) Inputs D Q FF D Q FF Input logic Ouput logic Count............ State reg....... Outputs ControllerDatapath State reg. or PC Control Mem temp1temp2 +/-+ Data RF RTL Architectures

11. Copyright  1999 Daniel D. Gajski IP-centric Specs S1S1 S3S3 S2S2 C Program ………….. SFSMDConcurrent, hierarchical SFSMD variable i, max: integer; max = 0; for i = 1 to 20 do if (A[i] > max) then max = A[i]; end if; end for; variable A: array[1..20] of integer Y A B C D e1e2 e3

12. Copyright  1999 Daniel D. Gajski Processor ControllerDatapath SR/PC Control MemRF temp1 temp2 IP CtrlDP IP IP-centric processorIP-centric system RF CtrlDP IP Processor IP-centric Architecture

13. Copyright  1999 Daniel D. Gajski IP-Centric Models IP BT W C Present Future

14. Copyright  1999 Daniel D. Gajski Reuse Explorations PET IP replicable at any time synthesizable behaviorwrapped IP behavior transducer Behavior IP Channel IP at any time virtual channel channel with IP protocol C C IP replicable

15. Copyright  1999 Daniel D. Gajski (a) Two synthesizable behaviors connected by a channel C A B AB (b) Synthesizable behavior connected to an IP (c) IP connected through an incompatible channel W A IP A BT T W C A A T Reuse Optimization Wrapper Resolution

16. Copyright  1999 Daniel D. Gajski CAD Methodology Capture – Simulate (60’s – 80’s) Describe – Synthesize (80’s – 00’s) Specify-Explore-Refine (00’s – 20’s)

17. Copyright  1999 Daniel D. Gajski Past, Present and Future Physical Logic Describe & Synthesize Specify, Explore & Refine Manufacturing Architecture Communications Manufacturing Functionality Connectivity Protocols Timing Describe Simulate Specs Design Manufacturing Capture & Simulate Algorithms Specs Algorithms (software) Executable Spec Algorithms Physical Logic Design Physical Logic Design

18. Copyright  1999 Daniel D. Gajski Manufacturing Describe Simulate Specs Algorithms (software) Physical Logic Design Present and Future Issues Issues: IP vs EDA Semi’ vs. Systems Simulation vs. Synthesis Hardware vs. Software VHDL vs. C Top-down vs. Bottom-up Integrated vs. Outsourced CE vs. CS Specify, Explore & Refine Architecture Communications Manufacturing Functionality Timing Describe & Synthesize Executable Spec Algorithms Physical Logic Design Connectivity Protocols

19. Copyright  1999 Daniel D. Gajski Specification model IP SW synthesis HW synthesis Manufacturing Validation of algorithm and functionality Estimation Simulation model Communication synthesis Communication model Architecture model IP Implementation model Validation of functionality and synchronization Estimation Validation of functionality and communication Estimation Validation of timing and performance Estimation Simulation model Simulation model Simulation model Synthesis flowAnalysis and validation flow Architecture exploration SpecC Methodology

20. Copyright  1999 Daniel D. Gajski Business Model Product, Knowledge System house Design house Manufacturing IP Providers EDA vendors Integrators Tools, Libraries Commodity IPs, Standard IPs, Star IPs Technology, Libraries

21. Copyright  1999 Daniel D. Gajski Business Model Product, Knowledge System house Design house Manufacturing IP providers EDA vendors Integrators Tools, Libraries, Commodity IPs, Standard IPs Star IPs Technology Scenario 1: Design world

22. Copyright  1999 Daniel D. Gajski Design house Business Model Product, Knowledge System house Manufacturing IP providers EDA vendors Integrators Tools Star IPs Technology, Libraries, Commodity IPs, Standard IPs Scenario 2: Split Design

23. Copyright  1999 Daniel D. Gajski Business Model Product, Knowledge, Assembly System house Manufacturing IP Providers EDA vendors Tools, Libraries Standard IPs, Star IPs, Commodity IPs Technology, Libraries Scenario 3: IP Providers World

24. Copyright  1999 Daniel D. Gajski Business Model Product, Knowledge System house Manufacturing IP providers EDA vendors Tools, Libraries, Commodity IPs, Standard IPs Star IPs Technology Scenario 4: Systems world

25. Copyright  1999 Daniel D. Gajski Top-down vs. Bottom-up Spec Layout Manuf. Virtual Comp. (soft) Spec Layout Manuf. Real Comp. (hard)

26. Copyright  1999 Daniel D. Gajski Reuse Paradigm New Languages, guidelines, extensions Models for exploration (spec, arch, comm, RTL) –Separation of computation & communication –Encapsulation IP automation standards Reuse automation (Synthesis with reuse) IP-centric methodology

27. Copyright  1999 Daniel D. Gajski Conclusion