1. Communication Between FPGA and LabView - FPGA part

2. Schematic of FPGA Program 2 Input Ports DAT/CMD ACLK ENA Output Ports Q ENAFB ACLKFB

3. Command Table 3 CMD(HEX)Subtrahend(H/B)Result(Binary)Meaning AA/1010 1010 A9/1010 1001 00 00 0001 Checking Status of FPGA B9/1011 100100 01 0000 Active 300MHz CLK BB/1011 101100 01 0010 Active 150MHz CLK BC/1011 110000 01 0011 Active 100MHz CLK CD/1100 110100 10 0100 Active 60MHz CLK CF/1100 111100 10 0110 Active 30MHz CLK D0/1101 000000 10 0111 Active 10MHz CLK ??Start SEU Test ??Send Back Result ??Memory Test