1. Project Overview: Nanoscale Application Specific ICs (NASIC) and Wire-Streaming Processors (WiSP) Csaba Andras Moritz Associate Professor University of Massachusetts, Amherst andras@ecs.umass.edu August 14, 2005

2. Copyright - Csaba Andras Moritz, ECE, UMass Amherst 2 NASIC and WISP Projects Objective  Explore novel circuits, architectures, suitable software approaches, and tools (CAD and simulation) as well as built-in fault tolerance approaches for designs on 2-D silicon nanowire (SiNW) and carbon nanotube (CNT) fabrics  Optimizations at various system layers to preserve fabric density without added requirements for manufacturing at nano-scale  Explore suitable architectures  Compare with aggressive deep-submicron CMOS designs  Explore new fabric models that overcome limitations discovered Collaborators  MassNanotech on nano devices and nanoscale fabrication  University of Brest in France on CAD tools for NASICs  6 other UMass ECE faculty on system work

3. Copyright - Csaba Andras Moritz, ECE, UMass Amherst 3 Motivation Little work on the benefits of SiNW and CNT based devices as building blocks for nanoscale systems. We are trying to answer questions like  What are the challenges when building nanoscale systems (e.g., circuits and architectures)?  Can the density advantages of nanodevices be preserved at system level? What would be the capabilities of such systems compared to CMOS systems at the end of the CMOS roadmap (like 30-nm and below)?  Influence device/manufacturing research based on insights gained?

4. Copyright - Csaba Andras Moritz, ECE, UMass Amherst 4 Outline Circuit-level work  Static NASICs  Dynamic NASICs  Nano Latches  Pipelining  Multi-tile design and pipelining Architectures  Wire Streaming (WISP)  Comparison with equivalent CMOS designs at 30-nm and below  Multi-tile designs Tools  Simplefit: performance comparison based on analytical models  Madeo: CAD prototyping tools for NASIC designs Papers Published

5. Copyright - Csaba Andras Moritz, ECE, UMass Amherst 5 Nanodevices Lauhon et al., Nature 420,57 Carbon Nanotubes (CNT) Silicon Nanowires (SiNW) Nanoarray Transistors or Diodes

6. Copyright - Csaba Andras Moritz, ECE, UMass Amherst 6 NASIC Circuit Work

7. Copyright - Csaba Andras Moritz, ECE, UMass Amherst 7 A Nanotile in Static NASICs microwires pullup network pulldow n network OR plane AND plane

8. Copyright - Csaba Andras Moritz, ECE, UMass Amherst 8 Sequential Circuits on Nanogrids The flip-flop has poor area efficiency.  Feedback loop requires turning corner on 2-D fabric It requires 2 doping types in each dimension. When cascading combinational circuits and flip-flops, diagonal effect further reduces area efficiency. An adder and a Flip-flop (pull up/down are not shown)

9. Copyright - Csaba Andras Moritz, ECE, UMass Amherst 9 Dynamic Circuits Dynamic circuits Precharge-Evaluate-Hold phase Hold phase for cascading dynamic circuits 10 01 1

10. Copyright - Csaba Andras Moritz, ECE, UMass Amherst 10 Dynamic NASIC tile and Pipeline Nano-Latch provides implicit latching on the SiNW  Dynamic circuit style with precharge- evaluate-hold control (see papers)  Solution for temporary data storage  Used to build pipelined structures high-density stream processing Pipelined structure

11. Copyright - Csaba Andras Moritz, ECE, UMass Amherst 11 Nano-Latch Cascaded dynamic circuits -> NanoLatch NanoLatch is implicit -> better area efficiency NanoLatch: idea for temporary storage

12. Copyright - Csaba Andras Moritz, ECE, UMass Amherst 12 Architecture

13. Copyright - Csaba Andras Moritz, ECE, UMass Amherst 13 Interconnection Neighboring NASIC tiles are connected by NWs while global interconnections are provided by MWs Note that only minor modifications and limited modifications to tiles are needed for efficient interconnect

14. Copyright - Csaba Andras Moritz, ECE, UMass Amherst 14 Pipeline Structure - An Example Pipelined 2-bit adder 2 bit adding processed in 2 stages

15. Copyright - Csaba Andras Moritz, ECE, UMass Amherst 15 Overview of WiSP WiSP – Wire-Streaming Processor Why WiSP?  Explore a nanoscale design at the circuit and architectural levels  It exercises most principles in NASICs NASIC circuits and principles for cascading and tiling Pipelining, dynamic circuits and nano latches  An architecture style that fits 2-D fabric constraints Requires minimal feedback and control Can use temporary storage on the wire, etc Features in the ISA help improve density

16. Copyright - Csaba Andras Moritz, ECE, UMass Amherst 16 Architecture of WiSP-0 WiSP-0 is the initial version of WiSP.  Supports simple ISA: nop, movi, mov, add, mul  Hazards exposed to compiler  Implements 5-stage pipeline on 5 NASIC nanotiles Floorplan of WiSP-0 Schematic of WiSP-0

17. Copyright - Csaba Andras Moritz, ECE, UMass Amherst 17 Program Counter (pull up/down and microwires are not shown) Bottom part is a 4- bit incrementer circuit Top part is a 4-bit nanolatch High density is achieved despite feedback path and latching

18. Copyright - Csaba Andras Moritz, ECE, UMass Amherst 18 Instruction ROM

19. Copyright - Csaba Andras Moritz, ECE, UMass Amherst 19 Register File

20. Copyright - Csaba Andras Moritz, ECE, UMass Amherst 20 ALU

21. Copyright - Csaba Andras Moritz, ECE, UMass Amherst 21 Comparison with 30-nm CMOS Area breakdown WiSP-0 Projected (1,000x1,000 tiles) Comparison with 30-nm CMOS 12.5X 115X Density Ratio

22. Copyright - Csaba Andras Moritz, ECE, UMass Amherst 22 Fault-tolerance Work Exploring built-in fault-tolerance Defect maps not required System level redundancy Simulation tools to evaluate yield

23. Copyright - Csaba Andras Moritz, ECE, UMass Amherst 23 Dynamic Style for Fault-tolerant Designs – FTD NASICs To use our built-in redundancy mechanism on dynamic nanotiles, we need to change the logic style: Use preDischarge-Evaluate-Hold phase on horizontal nanowires, but use preCharge-Evaluate- Hold phase on vertical nanowires

24. Copyright - Csaba Andras Moritz, ECE, UMass Amherst 24 Area Impact of Various FT Approaches Studied for WISP 2-level redundancy based on FTD NASIC logic S0 and S1 are other built-in circuit-level techniques

25. Copyright - Csaba Andras Moritz, ECE, UMass Amherst 25 Simulation and CAD Tools

26. Copyright - Csaba Andras Moritz, ECE, UMass Amherst 26 Initial System-Level Evaluation CMOSNASIC Technology30nm4nm pitched NW 90nm pitched MW Chip area1.8cm 2 # of transistors 10 9 variable We use SimpleFit (C.A.Moritz, et al 2001, IEEE Trans Par&Distributed Systems) extended for our circuit and nanodevice assumptions to evaluate the impact of density in a tiled NASIC architecture vs. 30-nm CMOS assuming same speed Assumptions

27. Copyright - Csaba Andras Moritz, ECE, UMass Amherst 27 CAD Tools for NASICs Developing NASIC MADEO  Physical modeling  Logic synthesis: combinational and sequential blocks  Architecture composing: binding blocks together to build operators, networks or processing elements,  Library management  Smalltalk based description We have created with our collaborators an initial version for NASICs

28. Copyright - Csaba Andras Moritz, ECE, UMass Amherst 28 Scaling of WISP ALU Designs Using NASIC Madeo

29. Copyright - Csaba Andras Moritz, ECE, UMass Amherst 29 Manual vs. NASIC Madeo RF Designs Manual Madeo

30. Copyright - Csaba Andras Moritz, ECE, UMass Amherst 30 Papers  “Wire-Streaming Processors on 2-D Nanowire Fabrics”, extended version of NSTI (Nano Science and Technology Institute) and NSC-3 papers, UMass Technical Report.  “Wire-Streaming Processors on 2-D Nanowire Fabrics”, NSTI (Nano Science and Technology Institute) Nanotech 2005, California, May 2005.  "Latching on the Wire and Pipelining in Nanoscale Designs", Non-Silicon Computation Workshop, in conjunction with ISCA-31  "Opportunities and Challenges in Application­Tuned Circuits and Architectures Based on Nanodevices", Computing Frontiers’04, ACM SIGMicro  "NASIC: Nanoscale Application-Specific ICs and Architectures", Boston Area Computer Architecture Workshop'04