1. Parking Pal Presentation #6 Team M1: Anna Kochalko Chris Moody Hong Tuck Liew John Wu Project Manager: Kartik Murthy October 10, 2007 Schematic Review! Your digital parking meter of the future!

2. Status Project Chosen Options explored and eliminated Wrote Java Implementation Specification defined Verilog obtained/modified Test Benches Schematic Design  Layout  Simulations

3. Mult/adder Car ~rate 60currentTime min hrs TeaEncryption Binary to BCD Main Mux (MM) AdderSubtractor Compare (max) (realTimeIn) /11 /6 /7 MM ticketTime /11 getTicket ID # 0 0 realTimeIn timeLimit timeInMin 0 7SegmentDisplay FlashMemory Charge rate TimeLeft /11 /1 /20 /1 /11 /7 BLOCK DIAGRAM startTime timeIn reg CarswipeIn getID Write_en timeInMin Charge getCharge (SRAM) start /1 /12 rate 0 TL2 TL2[10] 10 F(currentdate) addresses noCar10Min swipeOut noCar getTicket /1 10 timeLimit

4. Encryption Block Parts in Encryption Block:  2x 16 bits register  16 bits Mux  32 bits Mux  FSM(encryption)  Encryptor (Small Encryption Block)

6. Encryptor(Smaller Encryption Block) Parts in Encryptor  9 x 16 bit Adder  2 x 16 bit XOR with 3 inputs  2 x Left Shifter(<<4)  2 x Right Shifter(>>5)

8. Waveform

9. Tickets Block This block is responsible for determining how much time a car has left to park, and whether or not a car should be ticketed. Major Components: –11-Bit Adder, 11-Bit Subtractor, 11-Bit Comparator.

11. SRAM  Included in the following slides are simulation results for an SRAM cell and one of the adders.

15. SRAM Issues and Updates  Problems we ran into with the SRAM involved a problem with some inverters.  We originally put inverters in each SRAM cell, but this created errors in the outputs because it gave values to cells that should not have values attached to them. To solve this we changed the schematic to have a set of inverters at the end of the SRAM instead of throughout the cells. But this resulted in longer delays.  Some changes  We cleared up wasted logic - changed some of the 11 + 11 adders to 11+6 and 11+7  no carry out in adder

16. Overall Design Schematic

17. Things to Do SRAM FSM Binary to Serial Converter Power FSM Run Global Simulations