1. 15-447 Computer ArchitectureFall 2007 © November 7th, 2007 Majd F. Sakr msakr@qatar.cmu.edu www.qatar.cmu.edu/~msakr/15447-f07/ CS-447– Computer Architecture M,W 10-11:20am Lecture 19 Memory Hierarchy

2. 15-447 Computer ArchitectureFall 2007 © During This Lecture °Introduction to the Memory Hierarchy Processor Memory Gap Locality Latency Hiding

3. 15-447 Computer ArchitectureFall 2007 © The Big Picture Processor (active) Computer Control (“brain”) Datapath (“brawn”) Memory (passive) (where programs, data live when running) Devices Input Output Keyboard, Mouse Display, Printer Disk, Network

4. 15-447 Computer ArchitectureFall 2007 © Processor-DRAM Memory Gap (latency) µProc 60%/yr. (2X/1.5yr) DRAM 9%/yr. (2X/10 yrs) 1 10 100 1000 19801981198319841985198619871988198919901991199219931994199519961997199819992000 DRAM CPU 1982 Processor-Memory Performance Gap: (grows 50% / year) Performance Time “Moore’s Law”

5. 15-447 Computer ArchitectureFall 2007 © °SRAM: value is stored on a pair of inverting gates very fast but takes up more space than DRAM (4 to 6 transistors) Memories:

6. 15-447 Computer ArchitectureFall 2007 © DRAM: value is stored as a charge on capacitor (must be refreshed) very small but slower than SRAM (factor of 5 to 10) Word line Pass Transistor Bit line Capacitor Memories:

7. 15-447 Computer ArchitectureFall 2007 © °Users want large and fast memories! °SRAM access times are.5 – 5ns at cost of $4000 to $10,000 per GB. °DRAM access times are 50-70ns at cost of $100 to $200 per GB. °Disk access times are 5 to 20 million ns at cost of $.50 to $2 per GB. Memory 2004

8. 15-447 Computer ArchitectureFall 2007 © Storage Trends metric1980198519901995200020052005:1980 $/MB8,0008801003010.2040,000 access (ns)3752001007060508 typical size(MB) 0.0640.256416641,00015,000 DRAM metric1980198519901995200020052005:1980 $/MB19,2002,90032025610075256 access (ns)3001503515121030 SRAM metric1980198519901995200020052005:1980 $/MB50010080.300.050.00110,000 access (ms)877528108422 typical size(MB) 1101601,0009,000400,000400,000 Disk

9. 15-447 Computer ArchitectureFall 2007 © CPU Clock Rates 1980198519901995200020052005:1980 processor 8080286386PentiumP-IIIP-4 clock rate(MHz) 16201507503,0003,000 cycle time(ns)1,0001665061.30.33,333

10. 15-447 Computer ArchitectureFall 2007 © The CPU-Memory Gap The gap widens between DRAM, disk, and CPU speeds.

11. 15-447 Computer ArchitectureFall 2007 © Locality °Principle of Locality: Programs tend to reuse data and instructions near those they have used recently, or that were recently referenced themselves. Temporal locality: Recently referenced items are likely to be referenced in the near future. Spatial locality: Items with nearby addresses tend to be referenced close together in time. Locality Example: Data –Reference array elements in succession (stride-1 reference pattern): –Reference sum each iteration: Instructions –Reference instructions in sequence: –Cycle through loop repeatedly: sum = 0; for (i = 0; i < n; i++) sum += a[i]; return sum; Spatial locality Temporal locality

12. 15-447 Computer ArchitectureFall 2007 © Locality Example °Claim: Being able to look at code and get a qualitative sense of its locality is a key skill for a professional programmer. °Question: Does this function have good locality? int sum_array_rows(int a[M][N]) { int i, j, sum = 0; for (i = 0; i < M; i++) for (j = 0; j < N; j++) sum += a[i][j]; return sum; }

13. 15-447 Computer ArchitectureFall 2007 © Locality Example °Question: Does this function have good locality? int sum_array_cols(int a[M][N]) { int i, j, sum = 0; for (j = 0; j < N; j++) for (i = 0; i < M; i++) sum += a[i][j]; return sum; }

14. 15-447 Computer ArchitectureFall 2007 © Memory Hierarchy (1/3) °Processor executes instructions on order of nanoseconds to picoseconds holds a small amount of code and data in registers °Memory More capacity than registers, still limited Access time ~50-100 ns °Disk HUGE capacity (virtually limitless) VERY slow: runs ~milliseconds

15. 15-447 Computer ArchitectureFall 2007 © Memory Hierarchy (2/3) Processor Size of memory at each level Increasing Distance from Proc., Decreasing speed Level 1 Level 2 Level n Level 3... Higher Lower Levels in memory hierarchy As we move to deeper levels the latency goes up and price per bit goes down.

16. 15-447 Computer ArchitectureFall 2007 © Memory Hierarchy (3/3) °If level closer to Processor, it must be: smaller faster subset of lower levels (contains most recently used data) °Lowest Level (usually disk) contains all available data °Other levels?

17. 15-447 Computer ArchitectureFall 2007 © Memory Caching °We’ve discussed three levels in the hierarchy: processor, memory, disk °Mismatch between processor and memory speeds leads us to add a new level: a memory cache °Implemented with SRAM technology

18. 15-447 Computer ArchitectureFall 2007 © Memory Hierarchy Analogy: Library (1/2) °You’re writing a term paper (Processor) at a table in Library °Library is equivalent to disk essentially limitless capacity very slow to retrieve a book °Table is memory smaller capacity: means you must return book when table fills up easier and faster to find a book there once you’ve already retrieved it

19. 15-447 Computer ArchitectureFall 2007 © Memory Hierarchy Analogy: Library (2/2) °Open books on table are cache smaller capacity: can have very few open books fit on table; again, when table fills up, you must close a book much, much faster to retrieve data °Illusion created: whole library open on the tabletop Keep as many recently used books open on table as possible since likely to use again Also keep as many books on table as possible, since faster than going to library

20. 15-447 Computer ArchitectureFall 2007 © Memory Hierarchy Basis °Disk contains everything. °When Processor needs something, bring it into to all higher levels of memory. °Cache contains copies of data in memory that are being used. °Memory contains copies of data on disk that are being used. °Entire idea is based on Temporal Locality: if we use it now, we’ll want to use it again soon (a Big Idea)

21. 15-447 Computer ArchitectureFall 2007 © A View of the Memory Hierarchy Regs L2 Cache Memory Disk Tape Instr. Operands Blocks Pages Files Upper Level Lower Level Faster Larger Cache Blocks