1. Computer Systems Organization: Lecture 3
Ankur Srivastava
University of Maryland, College Park
Based on Slides from Mary Jane Irwin ( )
[Adapted from Computer Organization and Design,
Patterson & Hennessy, © 2005, UCB]
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2. Review: 2’s Complement Binary Representation
2’sc binary
decimal
1001 -7
1010 -6
1011 -5
1100 -4
1101 -3
1110 -2
1111 -1
0000
0001 1
0010 2
0011 3
0100 4
0101 5
0110 6
0111 7
Negate
1011
and add a 1
1010
complement all the bits
Signed numbers – assuming 2’s complement representation – for eight bits
Note that msb of 1 indicates a negative number, the bit string all 0’s is zero, that the largest positive number that can be represented is 7 (2**(n-1) –1 for n bits) whereas the largest negative number that can be represented is –8 (-2**(n-1) for n bits)
Note: negate and invert are different!

3. MIPS Number Representations
32-bit signed numbers (2’s complement): two = 0ten two = + 1ten ...
two = + 2,147,483,646ten two = + 2,147,483,647ten two = – 2,147,483,647ten ...
two = – 2ten two = – 1ten
MSB
LSB
Converting <32-bit values into 32-bit values
copy the most significant bit (the sign bit) into the “empty” bits > >
sign extend versus zero extend (lb vs. lbu)

4. Signed vs Unsigned Numbers
MIPS ALLOWS NUMBERS TO BE CONSIDERED BOTH AS SIGNED AND UNSIGNED
SIGNED NUMBERS CAN BE EITHER POSITIVE OR NEGATIVE, UNSIGNED NUMBERS CAN ONLY BE POSITIVE
sign extend versus zero extend (lb vs. lbu)
Lb loads a byte into the register assuming it is a signed number. Hence it extends the sign bit to fill up the rest of the bits.
Lbu: loads the byte assuming the number is unsigned, hence it fills the rest of the bits with zero
Similarly Lh and Lhu
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5. Signed vs Unsigned Numbers
Similarly Other Unsigned Instructions are Also Supported
Addu $s1 $s2 $s3
Subu $s1 $s2 $s3
Addiu $s1 $s2 CONSTANT
Sltu $s1 $s2 $s3
Sltiu $s1 $s2 CONSTANT
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6. MIPS Arithmetic Logic Unit (ALU)32
m (operation)
result A B
ALU 4
zero
ovf 1
Must support the Arithmetic/Logic operations of the ISA
add, addi, addiu, addu
sub, subu, neg
mult, multu, div, divu
sqrt
and, andi, nor, or, ori, xor, xori
beq, bne, slt, slti, sltiu, sltu
With special handling for
sign extend – addi, addiu andi, ori, xori, slti, sltiu
zero extend – lbu, addiu, sltiu
no overflow detected – addu, addiu, subu, multu, divu, sltiu, sltu

7. Review: A Full Adder How can we use it to build a 32-bit adder?
carry_in A B
carry_in
carry_out S 1 A
1-bit Full Adder S B
carry_out
S = A  B  carry_in (odd parity function)
carry_out = A&B + A&carry_in + B&carry_in
(majority function)
How can we use it to build a 32-bit adder?
How can we modify it easily to build an adder/subtractor?

8. A 32-bit Ripple Carry Adder/Subtractor
add/sub
1-bit FA S0
c0=carry_in c1 S1 c2 S2 c3
c32=carry_out
S31
c31
. . . A0 A1 A2
A31
Remember 2’s complement is just
complement all the bits
add a 1 in the least significant bit B0
control
(0=add,1=sub)
B0 if control = 0, !B0 if control = 1
A  B  +
For class handout

9. A 32-bit Ripple Carry Adder/Subtractor
add/sub
1-bit FA S0
c0=carry_in c1 S1 c2 S2 c3
c32=carry_out
S31
c31
. . . A0 A1 A2
A31
Remember 2’s complement is just
complement all the bits
add a 1 in the least significant bit B0
control
(0=add,1=sub)
B0 if control = 0, !B0 if control = 1
A  B  +
For lecture
1001 1
0001
1 0001

10. Overflow Detection
Overflow: the result is too large to represent in 32 bits
Overflow occurs when
adding two positives yields a negative
or, adding two negatives gives a positive
or, subtract a negative from a positive gives a negative
or, subtract a positive from a negative gives a positive
On your own: Prove you can detect overflow by:
Carry into MSB xor Carry out of MSB, ex for 4 bit signed numbers
For class handout 1 + 7 3 1 + –4
– 5

11. Overflow Detection
Overflow: the result is too large to represent in 32 bits
Overflow occurs when
adding two positives yields a negative
or, adding two negatives gives a positive
or, subtract a negative from a positive gives a negative
or, subtract a positive from a negative gives a positive
On your own: Prove you can detect overflow by:
Carry into MSB xor Carry out of MSB, ex for 4 bit signed numbers
For lecture
Recalled from some earlier slides that the biggest positive number you can represent using 4-bit is 7 and the smallest negative you can represent is negative 8.
So any time your addition results in a number bigger than 7 or less than negative 8, you have an overflow.
Keep in mind is that whenever you try to add two numbers together that have different signs, that is adding a negative number to a positive number, overflow can NOT occur.
Overflow occurs when you to add two positive numbers together and the sum has a negative sign. Or, when you try to add negative numbers together and the sum has a positive sign.
If you spend some time, you can convince yourself that If the Carry into the most significant bit is NOT the same as the Carry coming out of the MSB, you have a overflow. 1 1 1 1 1 1 1 + 7 3 1 + –4
– 5
– 6 1 1 7

12. Tailoring the ALU to the MIPS ISA
Need to support the logic operation (and,nor,or,xor)
Bit wise operations (no carry operation involved)
Need a logic gate for each function, mux to choose the output
Need to support the set-on-less-than instruction (slt)
Use subtraction to determine if (a – b) < 0 (implies a < b)
Copy the sign bit into the low order bit of the result, set remaining result bits to 0
Need to support test for equality (bne, beq)
Again use subtraction: (a - b) = 0 implies a = b
Additional logic to “nor” all result bits together
Immediates are sign extended outside the ALU with wiring (i.e., no logic needed)

13. Shift Operations
Also need operations to pack and unpack 8-bit characters into 32-bit words
Shifts move all the bits in a word left or right
sll $t2, $s0, 8 #$t2 = $s0 << 8 bits
srl $t2, $s0, 8 #$t2 = $s0 >> 8 bits
op rs rt rd shamt funct
also have sllv, srlv, and srav
Notice that a 5-bit shamt field is enough to shift a 32- bit value 25 – 1 or 31 bit positions
Such shifts are logical because they fill with zeros

14. Shift Operations, con’t
An arithmetic shift (sra) maintain the arithmetic correctness of the shifted value (i.e., a number shifted right one bit should be ½ of its original value; a number shifted left should be 2 times its original value)
so sra uses the most significant bit (sign bit) as the bit shifted in
note that there is no need for a sla when using two’s complement number representation
sra $t2, $s0, 8 #$t2 = $s0 >> 8 bits
The shift operation is implemented by hardware separate from the ALU
using a barrel shifter (which would takes lots of gates in discrete logic, but is pretty easy to implement in VLSI)

15. Multiply
Binary multiplication is just a bunch of right shifts and adds n
multiplicand
multiplier
partial
product
array
can be formed in parallel and added in parallel for faster multiplication n
double precision product 2n

16. MIPS Multiply Instruction
Multiply produces a double precision product
mult $s0, $s1 # hi||lo = $s0 * $s1
Low-order word of the product is left in processor register lo and the high-order word is left in register hi
Instructions mfhi rd and mflo rd are provided to move the product to (user accessible) registers in the register file
op rs rt rd shamt funct
multu – does multiply unsigned
Both multiplies ignore overflow, so its up to the software to check to see if the product is too big to fit into 32 bits. There is no overflow if hi is 0 for multu or the replicated sign of lo for mult.
Multiplies are done by fast, dedicated hardware and are much more complex (and slower) than adders
Hardware dividers are even more complex and even slower; ditto for hardware square root

17. Division
Division is just a bunch of quotient digit guesses and left shifts and subtracts n n
quotient
dividend
divisor
partial
remainder
array
remainder n

18. MIPS Divide Instruction
Divide generates the reminder in hi and the quotient in lo
div $s0, $s1 # lo = $s0 / $s1
# hi = $s0 mod $s1
Instructions mfhi rd and mflo rd are provided to move the quotient and reminder to (user accessible) registers in the register file
op rs rt rd shamt funct
Seems odd to me that the machine doesn’t support a double precision dividend in hi || lo but it looks like it doesn’t
As with multiply, divide ignores overflow so software must determine if the quotient is too large. Software must also check the divisor to avoid division by 0.
Multu and Divu are instructions that perform unsigned multiplication and division

19. Representing Big (and Small) Numbers
What if we want to encode the approx. age of the earth?
4,600,000, or x 109
or the weight in kg of one a.m.u. (atomic mass unit)
or x 10-27
There is no way we can encode either of the above in a 32-bit integer.
Floating point representation (-1)sign x F x 2E
Still have to fit everything in 32 bits (single precision)
s E (exponent) F (fraction)
1 bit bits bits
Notice that in scientific notation the mantissa is represented in normalized form (no leading zeros)
The base (2, not 10) is hardwired in the design of the FPALU
More bits in the fraction (F) or the exponent (E) is a trade-off between precision (accuracy of the number) and range (size of the number)

20. IEEE 754 FP Standard Encoding
Most (all?) computers these days conform to the IEEE 754 floating point standard (-1)sign x (1+F) x 2E-bias
Formats for both single and double precision (remember the data types in C)
F is stored in normalized form where the msb in the fraction is 1 (so there is no need to store it!) – called the hidden bit
To simplify sorting FP numbers, E comes before F in the word and E is represented in excess (biased) notation
Single Precision
Double Precision
Object Represented
E (8)
F (23)
E (11)
F (52)
true zero (0)
nonzero
± denormalized number
± 1-254
anything ±
± floating point number
± 255
± 2047
± infinity
255
2047
not a number (NaN)
Book distinguishes between the representation with the hidden bit there – significand (the 24 bit version) , and the one with the hidden bit removed – fraction (the 23 bit version)

21. Floating Point Addition
Addition (and subtraction)
(F1  2E1) + (F2  2E2) = F3  2E3
Step 1: Restore the hidden bit in F1 and in F2
Step 1: Align fractions by right shifting F2 by E1 - E2 positions (assuming E1  E2) keeping track of (three of) the bits shifted out in a round bit, a guard bit, and a sticky bit
Step 2: Add the resulting F2 to F1 to form F3
Step 3: Normalize F3 (so it is in the form 1.XXXXX …)
If F1 and F2 have the same sign  F3 [1,4)  1 bit right shift F3 and increment E3
If F1 and F2 have different signs  F3 may require many left shifts each time decrementing E3
Step 4: Round F3 and possibly normalize F3 again
Step 5: Rehide the most significant bit of F3 before storing the result
Note that smaller significand is the one shifted (while increasing its exponent until its equal to the larger exponent)
overflow/underflow can occur during addition and during normalization
rounding may lead to overflow/underflow as well

22. MIPS Floating Point Instructions
MIPS has a separate Floating Point Register File ($f0, $f1, …, $f31) (whose registers are used in pairs for double precision values) with special instructions to load to and store from them
lwcl $f1,54($s2) #$f1 = Memory[$s2+54]
swcl $f1,58($s4) #Memory[$s4+58] = $f1
And supports IEEE 754 single
add.s $f2,$f4,$f6 #$f2 = $f4 + $f6
and double precision operations
add.d $f2,$f4,$f6 #$f2||$f3 = $f4||$f5 + $f6||$f7
similarly for sub.s, sub.d, mul.s, mul.d, div.s, div.d

23. MIPS Floating Point Instructions, Con’t
And floating point single precision comparison operations
c.lt.s $f2,$f4 #if($f2 < $f4) cond=1; else cond=0
And double precision comparison operations
c.lt.d $f2,$f #$f2||$f3 < $f4||$f cond=1; else cond=0
and branch operations
bclt #if(cond==1) go to PC+4+25
bclf #if(cond==0) go to PC+4+25