1. Chapter 5 – Field-Effect Transistors (FETs)
Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross section. Typically L = 1 to 10 m, W = 2 to 500 m, and the thickness of the oxide layer is in the range of 0.02 to 0.1 m.

2. Field-Effect Transistors (FETs)

3. Field-Effect Transistors (FETs)
FET basic operational theory FET basic operational theory
•The current controlled mechanism (drain current) is based on electric field established by the voltage applied to the control terminal (gate).
•Current is only conducted by only one type of carrier “ electrons or holes” (that is why sometimes FET is called unipolar transistors. Another type is the insulated gate FET or IGFET.
•Why MOS (Metal-Oxide) Transistors?
•Very small (smaller silicone area on the IC)
•Simple to manufacture
•No need for biasing resistors.
•Used in VLSI (very-large-scale integration)
•The enhancement type MOSFET is the most significant semiconductor devise available today.

4. Field-Effect Transistor (FET)
Metal-oxide semiconductor field-effect transistor (MOSFET) has been extremely popular since the late 1970s.
Compared to BJTs, MOS transistors:
Can be made smaller /higher integration scale
Easier to fabricate /lower manufacturing cost
Simpler circuitry for digital logic and memory
Inferior analog circuit performance (lower gain)
Most digital ICs use MOS technology
Recent trend: more and more analog circuits are implemented in MOS technology for lower cost integration with digital circuits in a same chip

5. Field-Effect Transistors (FETs) Device Structure
Four Terminals: Gate, Drain, Source, Body
Unlike the BJT, the MOSFET is normally constructed as a symmetrical device.
The name of Metal-Oxide-Semiconductor is apparent from the structure.
Typically, L = 0.15 to 10 µm, W = 0.3 to 500µm, the thickness of the oxide layer is in the range of 0.02 to 0.1 µ m.
The minimum value of L achievable in a particular MOS technology is often referred as the feature size of the technology.
State-of-the-art: Intel Pentium 4uses 0.13 µm technology
Modern technology uses poly-silicon which has high conductivity, instead of metal to form the gate.

6. Physical Operation of Enhancement MOSFET
Operation with No Gate Voltage
With no bias applied to the gate, two back-to-back diodes exist in series between drain and source. The two back-to-back diodes prevent current conduction from drain to source when a voltage vDS is applied. The resistance is of the order of 10^12 ohms
Creating a Channel for Current Flow
If S and D are grounded and a positive voltage is applied to G, the holes are repelled from the channel region downwards, leaving behind a carrier-depletion region.
Further increasing VG attracts minority carrier ( electrons) from the substrate into the channel region. When sufficient amount of electrons accumulate near the surface of the substrate under the gate, an n region is created-called as the inversion layer.

7. Physical Operation of Enhancement MOSFET Applying a Small vDS
When a small potential is applied across the Gate and source, it pushes away the holes towards the substrate and attract electrons from the Drain and Source into the channel region. When sufficient electrons are formulated beneath the Gate area, current flows between the Drain and the Source. (Basically the holes are pushed away in N channel – NMOS type to be replaced by the electrons from both the Source and the Drain creating a channel of N majority causing current to flow from Drain to Source.

8. Physical Operation of Enhancement MOSFET
Applying a Small vDS
Applying a small vDS (~ 0.1 or 0.2 V) causes a current iD to flow through the induced nchannel from D to S.
The magnitude of iD depends on the density of electrons in the channel, which in turn depends on vGS.
For vGS = Vt (threshold voltage), the channel is just induced and the conducted current is still negligibly small.
As vGS > Vt, depth of the channel increases, iD will be proportional to (vGS – Vt), known as excess gate voltage or effective voltage.
Increasing vGS above Vt enhances the channel, hence it is called enhancement type MOSFET.
Note that iG=0.

9. Physical Operation of Enhancement MOSFET
Operation as vDS is Increased
vDS appears as a voltage drop across the channel.
Voltage across the oxide decreases from vGS at S to vGS-Vt at D.
The channel depth will be tapered, and become more tapered as vDS is increased.
Eventually, when vGS-vDS = Vt, the channel will be pinched off. Increasing vDS beyond this value has no effect on the channel shape and iD saturates (remains constant) at this value. The MOSFET enters the saturation region of operation.
vDSsat = Vgs- Vt

10. Physical Operation of Enhancement MOSFET
The drain current iD versus the drain-to-source voltage vDS for an enhancement-type NMOS transistor operated with vGS > Vt.

11. Field-Effect Transistors (FETs) - Enhancement Type
The enhancement-type NMOS transistor with a positive voltage applied to the gate. An n channel is induced at the top of the substrate beneath the gate.

12. Field-Effect Transistors (FETs) - Enhancement Type
An NMOS transistor with vGS > Vt and with a small vDS applied. The device acts as a conductance whose value is determined by vGS. Specifically, the channel conductance is proportional to vGS - Vt, and this iD is proportional to (vGS - Vt) vDS. Note that the depletion region is not shown (for simplicity).

13. Field-Effect Transistors (FETs) - Enhancement Type
Exercise 5.1

14. Field-Effect Transistors (FETs) - Enhancement Type
Exercise 5.1

15. Field-Effect Transistors (FETs) - Enhancement Type

16. Derivation of ID- vDS Relationship

17. Derivation of ID- vDS Relationship

18. Field-Effect Transistors (FETs) - Enhancement Type
Triode Region
Saturation Region
Derivation of the iD - vDS characteristic of the NMOS transistor.

19. Field-Effect Transistors (FETs) - Enhancement Type

20. Field-Effect Transistors (FETs)
Enhancement Type

21. Field-Effect Transistors (FETs) Enhancement Type
Cross section of a CMOS integrated circuit. Note that the PMOS transistor is formed in a separate n-type region, known as an n well. Another arrangement is also possible in which an n-type body is used and the n device is formed in a p well.

22. Field-Effect Transistors (FETs) Enhancement Type
(a) An n-channel enhancement-type MOSFET with vGS and vDS applied and with the normal directions of current flow indicated. (b) The iD - vDS characteristics for a device with Vt = 1 V and k’n(W/L) = 0.5 mA/V2.

23. Field-Effect Transistors (FETs) Enhancement Type
The iD - vGS characteristic for an enhancement-type NMOS transistor in saturation (Vt = 1 V and k’n(W/L) = 0.5 mA/V2).

24. Field-Effect Transistors (FETs) Enhancement Type
Increasing vDS beyond vDSsat causes the channel pinch-off point to move slightly away from the drain, thus reducing the effective channel length (by L).

25. Field-Effect Transistors (FETs) Enhancement Type
Effect of vDS on iD in the saturation region. The MOSFET parameter VA is typically in the range of 30 to 200 V.

26. Field-Effect Transistors (FETs)
Enhancement Type

27. Field-Effect Transistors (FETs)
Enhancement Type

28. Field-Effect Transistors (FETs) Enhancement Type
Large-signal equivalent circuit model of the n-channel MOSFET in saturation, incorporating the output resistance ro. The output resistance models the linear dependence of iD on vDS and is given by ro  VA/ID.

29. Field-Effect Transistors (FETs)
Enhancement Type

30. Field-Effect Transistors (FETs)
Enhancement Type

31. Field-Effect Transistors (FETs)
Enhancement Type – Practical Considerations

35. Field-Effect Transistors (FETs) Depletion Type
The depletion type MOSFET has similar structure to that the enhancement type MOSFET but with one important difference:
The depletion MOSFET has a physically implanted channel. Thus an n-channel depletion-type MOSFET has an n-type silicone region connecting the source and drain (both +n) at the top of the type substrate. Thus if a voltage vDS is applied between the drain and source, a current iD flows for vGS = 0 i.e there is no need to induce the channel.
The channel depth and hence its conductivity is controlled by vGS. Applying a positive vGS enhances the channel by attracting more electrons. The reverse when applying negative volt. The negative voltage is said to deplete the channel (depletion mode).

36. Field-Effect Transistors (FETs) Depletion Type
The current-voltage characteristics of a depletion-type n-channel MOSFET for which Vt = -4 V and k’n(W/L) = 2 mA/V2: (a) transistor with current and voltage polarities indicated; (b) the iD - vDS characteristics; (c) the iD - vGS characteristic in saturation.

37. Field-Effect Transistors (FETs) Depletion Type
vGS is positive the transistor will be operated in the enhancement mode enhancement mode
vGS is negative the transistor will be operated in the depletion mode. depletion mode.
The current-voltage characteristics of a depletion-type n-channel MOSFET for which Vt = -4 V and k’n(W/L) = 2 mA/V2

38. Field-Effect Transistors (FETs)
Depletion Type

39. Field-Effect Transistors (FETs)
Depletion Type

40. MOSFET Circuits at DC

41. MOSFET Circuits at DC

42. MOSFET Circuits at DC

43. MOSFET Circuits at DC

44. MOSFET As An Amplifier

45. MOSFET As An Amplifier

46. MOSFET As An Amplifier

47. MOSFET As An Amplifier

48. MOSFET As An Amplifier – Small-Signal Analysis

49. MOSFET As An Amplifier – Small-Signal Analysis

50. MOSFET As An Amplifier – The T Equivalent Circuit Models

51. MOSFET As An Amplifier – Modeling the Body Effect

52. MOSFET As An Amplifier – Exercise 5.17

53. MOSFET As An Amplifier – Exercise 5.18

54. MOSFET As An Amplifier – Exercise 5.19-20

55. Biasing a MOS Amplifier In Discrete Circuits

56. Biasing a MOS Amplifier In Integrated Circuits

57. Biasing a MOS Amplifier In Integrated Circuits

58. Biasing a MOS Amplifier In Integrated Circuits

59. Biasing a MOS Amplifier In Integrated Circuits

60. Basic Configurations of Single-Stage IC MOS Amplifiers

61. Basic Configurations of Single-Stage IC MOS Amplifiers

62. Basic Configurations of Single-Stage IC MOS Amplifiers

63. Basic Configurations of Single-Stage IC MOS Amplifiers

64. Basic Configurations of Single-Stage IC MOS Amplifiers

65. Basic Configurations of Single-Stage IC MOS Amplifiers

66. Exercises 5.22, 5.23, 5.25, 5.26, 5.27, 5.28.

67. The CMOS Digital Inverter

68. The CMOS Digital Inverter

69. The CMOS Digital Inverter

70. The CMOS Digital Inverter

71. The CMOS Digital Inverter

72. MOSFET As An Analog Switch

73. The MOSFET Internal Capacitances and High-Frequency Model

74. The Junction Field-Effect Transistor (JFET)

75. Gallium Arsenide (GaAs) Devices - MESFET

76. The Spice Model and Simulation Examples

85. Fig. 5.31 Conceptual circuit utilized to study the operation of the MOSFET as an amplifier.

86. Small-signal operation of the enhancement MOSFET amplifier.

87. Fig. 5.33 Total instantaneous voltages vGS and vD for the circuit in Fig. 5.31.

88. Fig Small-signal models for the MOSFET: (a) neglecting the dependence of iD on vDS in saturation (channel-length modulation effect); and (b) including the effect of channel-length modulation modeled by output resistance ro = |VA|/ID.

91. Fig. 5.37 the T model of the MOSFET augmented with the drain-to-source resistance ro.

94. Fig. 5.41 Basic MOSFET current mirror.

95. Fig. 5. 42 Output characteristic of the current source in Fig. 5
Fig Output characteristic of the current source in Fig and the current mirror of Fig for the case Q2 is matched to Q1.

98. Fig The CMOS common-source amplifier: (a) circuit; (b) i-v characteristic of the active-load Q2; (c) graphical construction to determine the transfer characteristic; and transfer characteristic.

105. Fig The CMOS common-gate amplifier: (a) circuit; (b) small-signal equivalent circuit; and (c) simplified version of the circuit in (b).

107. Fig The source follower: (a) circuit; (b) small-signal equivalent circuit; and (c) simplified version of the equivalent circuit.

111. Fig (a) NMOS amplifier with enhancement load; (b) graphical determination of the transfer characteristic; (c) transfer characteristic.

113. Fig The NMOS amplifier with depletion load: (a) circuit; (b) graphical construction to determine the transfer characteristic; and (c) transfer characteristic.

114. Fig Small-signal equivalent circuit of the depletion-load amplifier of Fig (a), incorporating the body effect of Q2.

115. Fig. 5. 55 (a) The CMOS inverter
Fig (a) The CMOS inverter. (b) Simplified circuit schematic for the inverter.

116. Fig Operation of the CMOS inverter when v1 is high: (a) circuit with v1 = VDD (logic-1 level, or VOH); (b) graphical construction to determine the operating point; and (c) equivalent circuit.

118. Fig Operation of the CMOS inverter when v1 is low: (a) circuit with v1 = 0V (logic-0 level, or VOL); (b) graphical construction to determine the operating point; and (c) equivalent circuit.

120. Fig. 5.58 The voltage transfer characteristic of the CMOS inverter.

122. Fig Dynamic operation of a capacitively loaded CMOS inverter: (a) circuit; (b) input and output waveforms; (c) trajectory of the operating point as the input goes high and C discharges through the QN; (d) equivalent circuit during the capacitor discharge.

123. Fig. 5.64 The CMOS transmission gate.

124. Fig Equivalent circuits for visualizing the operation of the transmission gate in the closed (on) position: (a) vA is positive; (b) vA is negative.

127. Fig (a) High-frequency equivalent circuit model for the MOSFET; (b) the equivalent circuit for the case the source is connected to the substrate (body); (c) the equivalent circuit model of (b) with Cdb neglected (to simplify analysis).

128. Fig. 5.68 Determining the short-circuit current gain Io/Ii.