1. AR2FL July 22, 2004 Anton, Campion, Mitch

2. Remaining Issues / Status One AR3FL board was stuffed in April by Godwin has been examined carefully. All locations readout and behave well on the detector. G1:summary excerpts from Log Investigating the board with a new cable. Chip 20- 100% occupancy 120/60 ohms - ok. 12k resistors that go to VCDS are present.  FIXED by inverting A-B lines on cable. Chip 21 - odd testpulse has an offset by 20 counts (both in tpscan and tphigh) Chip 23- channel 3 bad - low gain G2 : Chip 1 (1b) - channel 9 is low-gain; Chip 49, 50 wrong address Should be 33,34.

3. 300KHz Noise Rates No TP G1 G2

4. 300KHz On Module G1 G2

5. Clock Noise on Module G1 G2

6. G1:TPScan all Locations 10 test pulse cnts Test Pulse Even Channels Test Pulse Odd Channels

7. G2: TPScan: 10 test pulse cnts Test Pulse Even Channels Test Pulse Odd Channels

8. G1:AR2FL High Threshold Scan Odd ChannelsEven Channels ? On Bench

9. G1:AR2FL High Threshold Scan On Module Odd ChannelsEven Channels ?

10. G2:AR2FL High Threshold Scan On Module Odd ChannelsEven Channels

11. Temp and Voltage Tests G1 vdd=2.51 Chip Temp Vdd Vcc Vee 17 127 142 256 255 18 127 142 256 255 19 127 142 225 94 20 126 141 256 255 21 126 142 256 255 22 127 143 218 95 23 126 142 256 255 24 125 141 256 255 25 126 142 256 255 G2 Temp Vdd Vcc Vee 26 125 142 207 94 27 127 144 256 255 28 127 143 256 255 29 125 142 256 255 30 127 143 208 95 31 125 142 256 255 32 125 142 256 255 49 127 144 256 255 50 124 141 197 93

12. Shaper Select 0,0

13. Shaper Select 1, 1

14. Low Threshold Scan all Locations Odd Shaper 00 vs 11 (on Detector) G1 G2

15. AR2FL G1 Test Pulses Shaper 00 Shaper 11

16. AR2FL G2 Test Pulses Shaper 00 Shaper 11