1. Build-In Self-Test of FPGA Interconnect Delay Faults Laboratory for Reliable Computing (LaRC) Electrical Engineering Department National Tsing Hua University Adviser: Prof. Cheng-Wen Wu Student: Chun-Chieh Wang May 13, 2004

2. 2 Outline  Introduction  Island-style FPGA Architecture  Previous Work  The Proposed Method  Experimental Results  Conclusions and Future Work

3. 3 Introduction (1/2)  Field programmable gate arrays (FPGAs) have been wildly used.  Rapid prototyping and functional verification  Reconfigurable platform for many applications  Today’s FPGA  250,000 to millions equivalent gates  At higher speed beyond 100 MHz  FPGA could provide user-defined function in a system by its reconfigurable feature.

4. 4 Introduction (2/2)  FPGA delay-fault testing is becoming more important.  Many users implement more circuits operating at high speed in FPGA.  VDSM processes have resulted in more defects affecting the delays in the circuit.  The BIST is the trend of FPGA delay-fault testing.  At speed testing  Without require expensive ATE

5. 5 FPGA Architecture Classification  Island-style Xilinx Virtex Ⅱ,Altera 8K …  Hierarchy-style Xilinx XC6200, Prof. Huang’s FPGA … CLB

6. 6 Island-style FPGA  CLB  Configurable Logic Block  Interconnect  Global and local Interconnect  Wire Segments and CIPs (Configurable Interconnect Points)  I/O Block

7. 7 Configurable Interconnect Point

8. 8 Switch Matrix

9. 9 Hierarchical Routing Resources

10. 10 FPGA Manufacturing Testing  Application-independent  FPGA test classification  CLB Test  Interconnect Test  Approximately 80% of the transistors in an FPGA are dedicated to the routing resources. CLB TestInterconnect Test

11. 11 Fault Models of CLB Test  LUT: stuck-at faults in memory  Multiplexer: functional faults (stuck-on/stuck-off)  D flip-flop: functional faults  Input/Output lines: stuck-at faults Xilinx Spartan Series CLB

12. 12 Fault Models of Interconnect Test  CIPs: stuck-close (stuck-on) and stuck-open (stuck-off)  Wires stuck at 0/1, open wire, and shorted wires  Detecting the CIPs faults also detects stuck-at faults in configuration memory bits that control the CIPs

13. 13 Logic BIST Architecture Pass/Fail TPG #1 TPG #2 BIST Start BUT … … ORA … Row of TPGs Row of BUTs Row of ORAs Test Session #1 Row of BUTs Row of ORAs Row of TPGs Row of BUTs Test Session #2 TPG : Test Pattern Generator ORA : Output Response Analyzer BUT : Block Under Test source: VTS 96 “Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!)

14. 14 Interconnect BIST Architecture (1/2) source: ITC1998 ” Built-in self-test of FPGA interconnect “ 1 1 1 1 0 00 0 1 1

15. 15 Interconnect BIST Architecture (2/2) source:ITC2000 “Novel technique for built-in self-test of FPGA interconnects”

16. 16 Oscillator-Loop Method  The first BIST-based delay-fault testing approach for FPGAs. source:2002 IEEE Int’l On-Line Testing Workshop “BIST-Based Delay-Fault Testing in FPGAs”

17. 17  The traditional path delay fault model is not practicable for FPGA manufacturing testing since it is application-independent. Single-Line-Segment delay fault model  At speed testing BIST approach  The comparison-based BIST architecture only could detect the maximum difference between PUTs. Compare with the clock FPGA Delay-Fault Testing Issue

18. 18 Single-Line-Segment Delay Fault Model  Single-line-segment delay fault  The delay of a line segment is large enough to cause some paths covering this line segment exceeds some specified duration. ~ ylpeng ‘s thesis  The total number of faults = The total number of segments.

19. 19 Slack vs. Fault Size  PUT has different ability to detect fault due to the different length of PUT.  For getting the best detectability, we should make PUT as short as possible.

20. 20 The Basic Idea and Implement Issue  The clock skew effect should be considered and be tested before our test.

21. 21 1 st BIST Circuit (Rising Transition) Assumption : 1.T Q1→D2 < T Q1→D1 2.T Q2→EC < T Q1→D1 3.Ignore the clock skew between two F.F.s The logical value of Q1 Normal 1 → 0 → 1 Faulty 1 → 0 → 0 0 → 10 → 1 1 → 0 → 1 → 0 1→ 0 → 11→ 0 → 1 1 → 0 → 1 1 → 1 → 01 → 1 → 0

22. 22 1 st BIST Circuit (Falling Transition) Assumption : 1.T Q1→D2 < T Q1→D1 2.T Q2→EC < T Q1→D1 3.Ignore the clock skew between two F.F.s The logical value of Q1 Normal 0 → 1 → 0 Faulty 0 → 1 → 1 0 → 10 → 1 0 → 1 → 0 → 1 0 → 1 → 00 → 1 → 0 1 → 0 → 11 → 0 → 1 1 → 1 → 01 → 1 → 0

23. 23 WE & NS Switch Testing Issue After 16 TCs, we have fully tested these components : All line segments (not involved with IOB) All NE, WS, WN, and ES switches (not involved with IOB) WE

24. 24 Consider the Clock Skew in the Test

25. 25 Clock Skew Test

26. 26 The 2 nd BIST Circuit The logical value of Q2 Normal 0 → 0 → 1 Faulty 0 → 0 → 0

27. 27 How to Reduce TCs (1/2)

28. 28 How to Reduce TCs (2/2)

29. 29 Test Flow

30. 30 Experimental Results  Target Device : Xilinx Spartan Series FPGA  We only consider the single-length line in our experiment.  36 Test Configurations BIST TypeTarget Segment (Target Fault)No. of TCs 1All line segments & NE, WS, WN, and ES switches 16 2The clock skew between 2 adjacent F.F.s4 2All WE, NS switch16

31. 31 Feature Coverage  Feature Coverage :  CLB Block Coverage : 100.000%  CLB Pin Coverage : 100.000%  I/O Pin Coverage : 0.000%  Track Coverage : 87.500%  Switch Coverage : 86.963%  Total Feature Coverage : 87.891%  Effective Feature Coverage for BIST:  CLB Block Coverage : 100.000%  CLB Pin Coverage : 100.000%  Track Coverage : 100.000%  Switch Coverage : 100.000%  Total Feature Coverage : 100.000%

32. 32 Effective F.C. vs. Fault Size  Assumptions  T segment_spec is uniform on each segment  T segment_slack = 10% of T segment_spec

33. 33 Conditional Delay Fault Coverage Sample Count: 1K Each Segment Spec: 3.5 ns Defect Count (mean): 1.3 Slack over Spec: 10% (.35ns) FPGA Size: 14x14 Defect Size(ns) Delay Fault Coverage 0.3597.06% 0.70 97.39% 1.0599.53% 1.4099.66% 1.7598.22% 2.1099.51% 2.4599.77% 2.80100% 3.15100% Index 1 2 3 4 5 6 7 8 9

34. 34 Conclusions and Future Work  We proposed a new BIST-based approach to FPGA interconnect delay-fault testing.  It could be easily implemented in the different FPGA architecture.  It is also independent of the end application and FPGA array size.  The test phase must be developed for a specific CLB and/or interconnect architecture.  Automatic configuration generation for FPGA test is useful and needful.