1. Using Contrapositive Law to Enhance Implication Graphs of Logic Circuits Kunal K Dave Master’s Thesis Electrical & Computer Engineering Rutgers University 4/23/2004

2. Kunal Dave - Dept. of ECE2 Talk Outline Background Oring Nodes New Algorithms Results Conclusion and Future Work

3. 4/23/2004Kunal Dave - Dept. of ECE3 Background Implication graph-based ATPG techniques:  Larrabee et al. -- IEEE-TCAD, 1992  Chakradhar et al.-- IEEE-TCAD, 1993  Tafershofer et al. -- IEEE-TCAD, 2000 Implication based fault-independent redundancy identification techniques:  Iyer and Abramovici – IEEE-VLSI Systems, 1996  Agrawal et al. -- ATS, 1996  Gaur et al. -- DELTA, 2002  Mehta et al. -- VLSI Design, 2003

4. 4/23/2004Kunal Dave - Dept. of ECE4 Implication Graph An implication graph (IG)  Digital circuit in the form of a set of binary and higher-order relations. a b c Boolean equation AND: c = ab Boolean false function * AND: ab c = 0 ac + bc + abc = 0 Λ3Λ3 a b c c b a Λ1Λ1 Λ2Λ2 * Chakradhar et al. -- IEEE-D&T, 1990

5. 4/23/2004Kunal Dave - Dept. of ECE5 Observability Implications b OaOa OcOc Λ3Λ3 b b Λ1Λ1 Λ2Λ2 OcOc OaOa OcOc OaOa b a s OsOs OsOs O sa O sb Observability nodes – Agrawal, Lin and Bushnell -- ATS, 1996

6. 4/23/2004Kunal Dave - Dept. of ECE6 Redundancy Identification Obtain an implication graph from the circuit topology and compute transitive closure. There are 8 different conditions on the basis of which a fault is said to be redundant.* Examples:  If node c implies c then s-a-0 fault on line c is redundant.  If node O c implies O c then c is unobservable and both s-a- 0 and s-a-1 faults on line c are redundant. * Agrawal et al. -- ATS, 1996 & Gaur et al. -- DELTA, 2002

7. 4/23/2004Kunal Dave - Dept. of ECE7 Motivation – Problem Statement Implication graph (IG)  Digital circuit represented as a set of binary and higher-order relations. Binary relations  full implication edges. Higher-order relations  partial implications using anding nodes. Incomplete representation, can be improved. An improvement--use contrapositive rule to derive new partial implication nodes, oring nodes, to incorporate more complete logic information in the implication graph.

8. 4/23/2004Kunal Dave - Dept. of ECE8 Oring Nodes Expansion of Boolean false function AND : ac + bc + abc = 0 a c c a Contrapositive b c c b Contrapositive (a Λ b) cc (b V c) Contrapositive c (b V c) De-Morgan (a Λ c) bb (a V c) Contrapositive b (a V c) De-Morgan (b Λ c) aa (b V c) Contrapositive a (b V c) De-Morgan

9. 4/23/2004Kunal Dave - Dept. of ECE9 Use of Oring Nodes V1V1 a b c c b a Λ1Λ1 Λ2Λ2 a b c d d d V2V2

10. 4/23/2004Kunal Dave - Dept. of ECE10 Extended Use of Oring Node a b c d e s-a-0 Λ1Λ1 b d OcOc O ac Λ2Λ2 a b a V1V1

11. 4/23/2004Kunal Dave - Dept. of ECE11 Motivation - A Problem Statement Addition of a new edge can change the transitive closure (TC). Re-computation of TC is required. Algorithms are needed to update TC rather than re- computing it. Develop new algorithms that dynamically update the transitive closure graph while extracting implications from a logic network. Apply new implication graph and new dynamic update algorithms to redundancy identification to obtain better performances.

12. 4/23/2004Kunal Dave - Dept. of ECE12 Update routine (1) Update(G, v s, v n ){ (2) for each parent P i of source v s { (3) for each child C j of destination v n { (4) if (edge P i  C j does not exist) (5) addTcEdge(P i, C j ); (6) } } }//Update b c d a Nodes Parents Nodes Child Nodes a aa, b, d b b, ab c cc, d d d, a, cd

13. 4/23/2004Kunal Dave - Dept. of ECE13 Update_Partial_A Converts partial implications in to possible full implications using anding nodes. New edge, v s  v d, added???  Check if v d is a parent of an anding node Λ x.  Find a common grandparent G p of the node Λ x.  Add TC edge from G p to successor( Λ x ). e c d a Λ1Λ1

14. 4/23/2004Kunal Dave - Dept. of ECE14 Update_Partial_AO Converts partial implications in to possible full implications using oring nodes. New edge, v s  v d, added???  Check if v s is a child of an oring node V x.  Find a common grandchild G c of the node V x.  Add TC edge from predecessor(V x ) to G c. e c d a V1V1

15. 4/23/2004Kunal Dave - Dept. of ECE15 Update_Partial_AO (contd…) Also obtains backward partial implications using oring nodes that were previously obtained by extra anding nodes. c d e Λ1Λ1 b d OcOc O ac Λ2Λ2 a b a V1V1 a b s-a-0

16. 4/23/2004Kunal Dave - Dept. of ECE16 An Example w x m p n b a c z n m V1V1 Λ1Λ1

17. 4/23/2004Kunal Dave - Dept. of ECE17 Number of Partial Nodes

18. 4/23/2004Kunal Dave - Dept. of ECE18 Results on ISCAS Circuits Circuit Total faults Redundant faults identified and run time TRANFIRETC M Our Algorithm Red. faults CPU Sec. Red. Faults CPU Sec. Red. Faults CPU Sec. Red. Faults CPU Sec. c19081879713.061.823.255.7 c2670274711595.2291.5594.0696.0 c75527550131308.0304.75111.56517.7 c123813556917.461.9202.6515.4

19. 4/23/2004Kunal Dave - Dept. of ECE19 ISCAS ’85 -- C1908 979 887 74 s-a-1 952 953 949 926 s-a-1 Redundant faults

20. 4/23/2004Kunal Dave - Dept. of ECE20 ISCAS ’85 -- C5315 1 0/1 1 1 1 1 1 PI PO 0 0 0 0 0/1 0 1 1 1 Redundant fault

21. 4/23/2004Kunal Dave - Dept. of ECE21 ISCAS ’85 -- C5315 1 0/1 1 0 0 0 1 PI PO 1 1 1 0/1 0 1 0 Redundant fault

22. 4/23/2004Kunal Dave - Dept. of ECE22 Conclusion – Future Work Contributions of thesis  New partial implication structure called oring node enhances implication graph of logic circuits; more complete and more compact the the graph with just anding nodes.  New algorithms dynamically update the transitive closure every time a new implication edge is added; greater efficiency over complete recomputation.  New and improved fault-independent redundancy identification. New techniques can be further explored in following areas:  Fanout stem unobservability – proposed solution  Equivalence checking  Test generation

23. 4/23/2004Kunal Dave - Dept. of ECE23 Thank You