1. UPC Value Compression to Reduce Power in Data Caches Carles Aliagas, Carlos Molina and Montse García Universitat Rovira i Virgili – Tarragona, Spain {caliagas, cmolina, mgarciaf}@etse.urv.es Antonio González and Jordi Tubella Universitat Politècnica de Catalunya – Barcelona, Spain {antonio,jordit}@ac.upc.es Europar´03, Klagenfurt - August 26-29, 2003

2. Motivation Caches spend close to 50% of total die area Caches may be responsible for 10% to 20% of total power dissipated by a processor

3. Cache Storage TAG DATA Cache Line address TAG Comparison Cache access HIT Value

4. Structures Accessed TAG DATA Cache Line address TAG Comparison Cache access HIT Value

5. Useful Information TAG DATA Cache Line address TAG Comparison Cache access HIT Value

6. Compressed Data TAG Cache Line address TAG Comparison HIT Value 30% of total capacity Compressed Data Value decompression

7. Objective Reduction of: Die area. Energy consumption. Maintaining: Miss ratio. Latency.

8. Compression Types Integer compression The value is an integer. The compression applied is: –Sign extension. –“0” bit elimination. Address compression The value is a pointer. From pointer to pointer only few bits are different. Address are: –Data pointers, code pointers and stack pointers Try to recognize a common pattern. The patterns are stored on a common structure. Only the different bits are stored in cache.

9. Integer Compression Six different compression forms, depending on significant bits position. Two 32-bit words or one 64-bit word 0 0 0 0 0 T1: T2: T3: T4: T5: T6:

10. Address Compression One compression type Pointer pattern + variable bits. Several patterns stored in a separate table: Address Table (AT) Only 8 patterns represents 83%. 0 TA: Pattern 0 0 Pattern-1 Pattern-2 Pattern-3 Pattern-k

11. Data Value Compression Close to 70% of all data stored in a 16KB data cache can be compressed from 64 to 22 bits. Percentage of each type of compression applied

12. Simulation Enviroment Simulators Cacti tool version 3.0 (Static Analysis) Alpha version of SimpleScalar 3.0 (Dynamic Analysis) Benchmarks Spec2000 Maximum Optimization Level DEC C & F77 compilers with -non_shared -O5 Statistics Collected for 1 billion instructions Skipping initializations

13. - Integer type compression - Address pattern index - Non compressed The Pattern Cache Direct access 4 bytes Address Location Word: 8 bytes LT Tag Line 32 bytes AB VT AT Address Pattern Pointer Free bit map 13 bits 4x 22bits - Compressed value or - Pointer to uncompressed value

14. Cache Behavior Data access HITMISS Integer compression Address compression Non compressed Integer comp. Address comp. Non comp. 75%25% 93%7% 70%23% Static analysis Next Level cache + Dynamic analysis

15. Static analysis Base cache: Direct mapped 16KB, 32Bytes/line. Pattern Cache: Same associative and number of lines. LT Three configurations reducing the area of VT to 40%, 30% and 20% of the original data area. AT: 8 entries. Assist Buffer: –Full associative cache of 16 entries –Working as a Victim cache in the Base cache.

16. Die Area

17. Access Time

18. Energy Consumption

19. Dynamic Analysis Energy consumption of 1 st level cache plus 2 on Level cache: EC = (Hit * DL1_EC) + (Miss * (2 * DL1_EC+ DL2_EC)) 1st level cache: 64KB to 4KB 2on level cache: 512KB

20. Energy Consumption (2)

21. Results Caches ranging from 4KB to 64KB

22. Conclusions High degree of value compression can be applied in data caches. The compression allow to store the same information with less die area. This involves an energy consumption reduction. While maintaining the same access time. With minor miss ratio increment.

23. UPC Value Compression to Reduce Power in Data Caches Carles Aliagas, Carlos Molina and Montse García Universitat Rovira i Virgili – Tarragona, Spain {caliagas, cmolina, mgarciaf}@etse.urv.es Antonio González and Jordi Tubella Universitat Politècnica de Catalunya – Barcelona, Spain {antonio,jordit}@ac.upc.es Europar´03, Klagenfurt - August 26-29, 2003