1. HSDSL, Technion Winter 2008 Characterization Presentation on: Skew And Jitter Generating And Measuring System For High Speed Experiments Undergraduate Project By: Bassel Massad Wasseem Zaher 5th March 2008

2. Agenda Definitions Project: Background And Objective System Architecture: Top Level System Analysis: Anchor Element Time Table: What next?

3. Definition: Skew A Constant Time Delay phenomenon.  sec  Signal Skewed Signal Skew Range intended: few nanoseconds

4. Definition: Jitter Deterministic/Random Time delay, following a function of time. Jitter Wanted (ideal) Signal Possible Real Signals Time [sec] Signal [Volt] Usually unwanted phenomenon Classified into categories (Random, Deterministic, Periodic… more Details ahead) Each Category is treated differently in both Generating and Measuring techniques.

5. Agenda Definitions Project: Background And Objective System Architecture: Top Level System Analysis: Anchor Element Time Table: What next?

6. Project: Background And Objective Project Objective: Design a high speed experiments array for Generating and Measuring Skew and Jitter phenomena Background: A Variety of 60 High Speed Experiments distributed to 15 groups of which the user chose. Source High Speed Experiments Unit ****** ****** Samplers General Control Unit Measuring Unit Experiments LUT  Our Mission: Designing A System which knows to do the following: Generating Skew Generating Jitter Measuring Skew Measuring Jitter

7. Agenda Skew Definition Jitter Definition Project: Background And Objective System Architecture: Top Level System Analysis: Anchor Element Time Table: What next?

8. Generating System Controller Measuring system Next Skew/Jitter Subsystem Architecture Starting Point: Contains Initial restrictions and compatibility demands source

9. Inputs from Controller source Programmable Delay Chip Skew / Jitter Reference Measuring System Generating Unit Back To Controller מפצל שעון

10. Frequency Manipulation Source From Generating Unit (Frequency=F 0 ) Commands form Users Generating System Controller Encoding LUT Back F/n Memories Array Memories Control (Addresses, Memories selection…) n Select

11. 54642A Oscilloscope Agilent GPIB computer Measuring System Generating System Back General Purpose Interface BUS

12. Agenda Definitions Project: Background And Objective System Architecture: Top Level System Analysis: Anchor Element Time Table: What next?

13. Generating Unit Analysis Basis: source Manipulated to fit: –5MHz Differential Signal –Duty Cycle = 50% –Short Rise/Fall Times (~300ps) –  Maximal Delay Chip Frequency follows 3x300ps Cycle time (Roughly 1.11GHz) Delay element: On Semiconductor’s MC100EP195B Suggested –Programmable Range: 0ns to 10ns –Resolution : 10psec Increments –LVPECL Compatible IO V CC = [3.0v, 3.6v] –Max Frequency: 1.2GHz –Worst Case Timing: »Worst Case Timing: Max{t s +t h }+Max{t PLH,t PHL }<16ns <T cycle /2 »  Gives the impression we are to control cycle-to-cycle Jitter! Tcycle=200ns Analyze the system reverse- ward: First show how we design the 195 with its environment

14. Agenda Definitions Project: Background And Objective System Architecture: Top Level System Analysis: Anchor Element Time Table: What next?

15. Time Table 1 st weak 2 nd weak 3 rd weak 4 th weak 5 th weak Characterization Presentation Midterm Presentation Memories: Study and Design חקירת דרכי מדידה ותיאומם עם המערכת / בניית מחלקי תדר לשאול את יוסי מצגת בניית מצביעים