1. Realizations of CMOS Fully Differential Current Followers/Amplifiers by Hussain Alzaher and Noman Tasadduq Electrical Engineering Department King Fahd University of Petroleum & Minerals Dhahran, Saudi Arabia

2. 2 Outline  Objectives  Introduction Why fully differential architecture? Defining Current amplifier (CA)/Current Follower (CF)  Low Power CMOS Realization of CA/CF  Fully Differential Current Amplifier (CA)  Fully Differential CA Topologies Topology ‘a’ Topology ‘b’ Topology ‘c’  Simulation Results Biasing conditions DC responses AC responses Common mode responses Monte-Carlo analysis  Application Example Fully differential Sallen-Key highpass filter AC response  Conclusion

3. 3 Objective  Present fully differential CF/CA topologies.  Investigate their characteristics.  Compare and identify the best topology.  Confirm the results using simulation.  Give an application example.

4. 4 Introduction Why Fully Differential Architecture? Fully differential architectures are essential to enhance the performance of mixed signal applications in terms of  Supply noise rejection.  Dynamic range.  Harmonic distortion.

5. 5 Introduction  Theory behind fully differential opamp realization is well established.  Current Amplifier is the core analog building block for current mode circuits. Its fully differential realization is still under research.

6. 6 Introduction Current Amplifier (CA)/Current Follower (CF)  Conveys input current from a low impedance input terminal (X) to a high impedance output terminal (Z).  For a CA, current is conveyed with gain K.  CF is a special case of CA in which gain (K) equals one.  Can be classified as positive (input and output currents are both going in the same direction) or the negative type (having currents in opposite directions). CA with +ve output CA with -ve output

7. 7 Low Power Current Amplifier Single Input Dual Output Class-AB CA/CF I zp = -I zn = KI x V x =0

8. 8 Fully Differential CA (FDCA)  Four terminal device, with two input and two output currents.  Differential output current can be expressed as,  Ideally, A cm = 0.

9. 9 FDCA Topologies Topology ‘a’ Topology ‘b’ Topology ‘c’ A diff =2K A diff =K

10. 10 FDCA Topologies Topology ‘a’ Non-ideal Differential mode gain Non-Ideal Common mode gain  Error in K p1 causes finite common mode output.  When current gain K p1 is represented by first order lowpass model, common-mode gain exhibits highpass response.  Not suitable for high frequency applications. Disadvantages Advantages  Lowest power consumption as compared to other two topologies. i.e. if, and CF1 ideal

11. 11 FDCA Topologies Non-ideal Differential mode gain Non-ideal Common mode gain  Slightly higher power consumption than topology ‘a’.  Lower output resistance as compared to topologies ‘a’ and ‘c’. Disadvantages Topology ‘b’ Advantages  Lower power consumption than topology ‘c’.  Widest bandwidth (as will be shown in simulation results)  Symmetric input and output resistances.

12. 12 FDCA Topologies Non-ideal Differential mode gain Non-ideal Common mode gain  Highest power consumption.  Most no. of active elements. Ideal differential gain Disadvantages Advantages  Smallest input R.  Output R= twice that of ‘b’ Topology ‘c’ I o = K(I 1b -I 2a )-K(I 2b -I 1a )=K(I 1b +I 1a )-K(I 2a +I 2b )=K(I 1 -I 2 ) I o1 =K(I 1b -I 2a ) and I o2 = K(I 2b -I 1a )

13. 13 Simulation Results Biasing Conditions  TSMC 0.18  m CMOS process.  Supply voltage = ±1.5V.  I BP =40µA and I SB =10µA.

14. 14 Simulation Results Differential-mode DC operation for the three topologies All three topologies have comparable DC performance

15. 15 Simulation Results Differential-mode AC response for the three topologies Topology ‘a’ 57MHz Topology ‘b’ 77MHz Topology ‘c’ 36MHz Topology ‘b’ has the widest bandwidth

16. 16 Simulation Results Ideal Common-mode AC responses Topology ‘b’ and ‘c’ have excellent common-mode response. Topology ‘a’ has common mode gain dependent on frequency.

17. 17 Simulation Results Monte-Carlo Analysis Effect of CA mismatches on the common-mode rejection. Topology ‘a’  exhibits average A cm of -37.5dB, -45dB, -50dB, -56dB, and - 65dB in the presence of mismatches of 2%, 1%, 0.5%, 0.2%, and 0.1%, respectively. Topology ‘b’  Extremely low (-110dB) even with 2% mismatch.  Constant over the entire differential-mode bandwidth. Topology ‘c’  A cm frequency dependent in the presence of mismatches.  Increases as frequency increases  Maintains an acceptable value of -47dB at a frequency of 10MHz.

18. 18 Application Example Fully Differential Current-Mode Sallen-Key Highpass filter Using Topology ‘b’

19. 19 Application Example Magnitude response of the Sallen-Key Highpass filter Results in good agreement

20. 20 Application Example Sallen-Key Highpass filter Previous example demonstrates that replacing voltage- mode circuit by current-mode provides wider bandwidth. Notice that the non-ideal roll-off starts at 30MHz, while it usually comes much earlier in voltage-mode realizations.

21. 21 Conclusion Topology ‘a’ +: Least power consumption. - : Freq. dependent A cm. Topology ‘c’ +: Best R in and R out. - : Power consumption and area are highest. - : Differential-mode bandwidth is narrowest. - : Mismatch results show freq. dependent A cm. Topology ‘b’ -+: Consumes slightly more power than ‘a’ but much lower than ‘c’. +: Widest differential-mode bandwidth. +: Frequency independent common-mode gain.  Best solution for high freq. applications.

22. 22 Important Notes  It is well known that current-mode signal processing has the potential advantages of higher bandwidth and wider signal swing, compared with their voltage-mode counterparts.  This work highlights these advantages and demonstrates a new advantage, which is the simplicity of FDCA realizations compared with FDVF realizations.  So far, FDVF realizations has been inefficient (comparison can be seen in the following references). [1] M. Youssef, and A. Soliman, “A novel CMOS realization of differential input balanced output current operational amplifier and its applications,” Analog Integrated Circuits and Signal Processing, vol. 44, pp. 37-53, 2005. [2] H. Alzaher, M. Al-Ghamdi, and M. Ismail, “A CMOS Low Power Bandpass IF Filter for Bluetooth,” IET Circuits, Devices & Systems, vol. 1, pp. 7 – 12, 2007.

23. 23 THANK YOU