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Design of Asynchronous Circuits Materials from Falkowski.

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1 Design of Asynchronous Circuits Materials from Falkowski

2 Design of asynchronous circuits In general, here is the flow of processing. Natural Language specification Timing diagram of input and output signals Graph of transitions and outputs

3 Design of asynchronous Machine Create the initial transition table Reduce the initial transition table Encode rows of reduced table Determine output functionsDetermine transition function

4 Reduction of pseudo-equivalent states and equivalent states x1x0x1x0 00011110y2y1y0y2y1y0 S a ab-g0-- b -bc-101 c -ec-1-1 d db-g0-0 e -ef- f --fg11- g d-fg000 h ahf--11 i --ji000 j -hj-11- Stable statesNon-stable states Equivalent states a-d Compatible outputs Consistent outputs Equivalent state dashes

5 Reduction of equivalent (compatible) states and pseudo-equivalent states x1x0x1x0 00011110y2y1y0y2y1y0 S a ab-g0-- b -bc-101 c -ec-1-1 d db-g0-0 e -ef- f --fg11- g d-fg000 h ahf--11 i --ji000 j -hj-11- Conditionally compatible states b-e condition c=f Compatible outputs Consistent outputs Compatible state Condition dashes Conditionally compatible states g –i (condition f=j) dashes Consistent outputs Pseudo-equivalent states Compatible inputs Equivalent state condition dashes

6 Reduction of equivalent (compatible) and pseudo- equivalent states x1x0x1x0 00011110y2y1y0y2y1y0 S a ab-g0-- b -bc-101 c -ec-1-1 d db-g0-0 e -ef- f --fg11- g d-fg000 h ahf--11 i --ji000 j -hj-11- Pseudo-equivalent states c-f Compatible inputs Consistent outputs Pseudo-equivalent states dashes Consistent outputs Pseudo-equivalent states Compatible inputs Pseudo-equivalent states dashes Pseudo-equivalent states Pseudo-equivalent states f-j

7 Reduction of equivalent and pseudo-equivalent states x1x0x1x0 00011110y2y1y0y2y1y0 S a ab-g0-- b -bc-101 c -ec-1-1 d db-g0-0 e -ef- f --fg11- g d-fg000 h ahf--11 i --ji000 j -hj-11- States b-h Compatible inputs Inconsistent outputs States e-h Compatible inputs Inconsistent outputs

8 Results of reducing compatible and pseudo-equivalent states x1x0x1x0 00011110y2y1y0y2y1y0 S a,d ab-g0-0 b,e -bc-101 c,f -bc-111 g a-cg000 h ahc--11 i --ji000 j -hj-11- Compatible states a-d, conditionally compatible states b-e and pseudo-equivalent states c-f.

9 Reduction of compatible states of Moore Machine x1x0x1x0 00011110y2y1y0y2y1y0 S a,d ab-g0-0 b,e -bc-101 c,f -bc-111 g a-cg000 h ahc--11 i --ji000 j -hj-11- Compatible states a,d-g Consistent outputs

10 Result of reduction of compatible states for Moore Machine x1x0x1x0 00011110y2y1y0y2y1y0 S a,d,g ab-g000 b,e -bc-101 c,f -bc-111 h ahc--11 i --ji000 j -hj-11-

11 Reduction of compatible states of Mealy Machine x1x0x1x0 00011110y2y1y0y2y1y0 S a,d ab-g0-0 b,e -bc-101 c,f -bc-111 g a-cg000 h ahc--11 i --ji000 j -hj-11-

12 Results of reduction of compatible states of Mealy Machine x1x0x1x0 00011110 S a,b,c,d,e,f abcg g,h ahcg i,j -hji

13 Outputs in Moore Machine x1x0x1x0 00011110y2y1y0y2y1y0 S a,d,g ab-g000 b,e -bc-101 c,f -bc-111 h ahc--11 i --ji000 j -hj-11-

14 Outputs in Mealy Machine x1x0x1x0 00011110 S a,b,c,d,e,f abcg 0-0101111 g,h ahcg -11000 i,j -hji 11-000 x1x0x1x0 y2y1y0y2y1y0 S a,d 0-0 b,e 101 c,f 111 g 000 h -11 i 000 j 11- Outputs for stable states

15 Outputs in Mealy Machine x1x0x1x0 00011110 S a,b,c,d,e,f abcg 0-01011110-0 g,h ahcg 0-0-11 000 i,j -hji ----1-11-000 a  g  g 0-0  g  000 = 0-0 b  g  g 101  g  000 = -0- c  g  g 111  g  000 = - - - h  a  a -11  a  0-0 = - - - g  a  a 000  a  0-0 = 0-0 h  c  c -11  c  111 = - 11 g  c  c 000  c  111 = - - - i  h  h 000  h  -11 = - - - j  h  h 11-  h  -11 = - 1 - Outputs for non-stable states

16 Encoding an asynchronous machine x1x0x1x0 00011110y1y0y1y0 S a abad00 b dbbb01 c acbd11 d dcdd10 Moore Machine table

17 Races x1x0x1x0 00011110y1y0y1y0 S 00a abad 01b dbbb 10c acbd11 d dcdd10 a b cd 0001 1110

18 Elimination of races by cyclic coding ab c d 000 001 101 111 S 100 S S S 011 110 010 a b cd 0001 1110

19 ab c d 000 001 101 111 S 100 S S S 011 110 010 x1x0x1x0 00011110y1y0y1y0 S 000a aba10000 001b dbbb01 010 a0 - 011 b- 1 100 d- 0 101d dcdd10 110 010- 1 111c 110c011d11

20 Encoding of asynchronous Machine x1x0x1x0 00011110y1y0y1y0 S 000a 00100010000 001b101001 01 011--001-- 1 010000---0 - 110010---- 1 111c11011101110111 101d 111101 10 100---101- 0

21 Realization of memory and outputs We design an asynchronous circuit specified by a timing diagram. The method works for both Moore and Mealy.

22 Moore Machine – initial table 1/0 2/0 3/0 4/1 5/0 00 11 00 10 01 00 x1x0x1x0 011110Z S S1S1 S1S1 S2S2 --0 S2S2 S4S4 S2S2 S3S3 -0 S3S3 -S2S2 S3S3 -0 S4S4 S4S4 --S5S5 1 S5S5 S1S1 --S5S5 0 01 11 00 10

23 We reduce the equivalent states x1x0x1x0 00011110Z S S1S1 S1S1 S2S2 --0 S2S2 S4S4 S2S2 S3S3 -0 S3S3 -S2S2 S3S3 -0 S4S4 S4S4 --S5S5 1 S5S5 S1S1 --S5S5 0 Only states S 1 and S 4 are in the same column But these states have inconsistent outputs

24 Reduction of compatible states for Moore Machine x1x0x1x0 00011110Z S S1S1 S1S1 S2S2 --0 S2S2 S4S4 S2S2 S3S3 -0 S3S3 -S2S2 S3S3 -0 S4S4 S4S4 --S5S5 1 S5S5 S1S1 --S5S5 0 For Moore Machine, compatible are states S 1, S 3 and S 5. These states have consistent outputs. State S 2 does not belong to this group because it includes state S 4, which has inconsistent output with respect to remaining states x1x0x1x0 00011110Z S S 1,S 3, S 5 S1S1 S2S2 S3S3 S5S5 0 S2S2 S4S4 S2S2 S3S3 -0 S4S4 S4S4 --S5S5 1 After reduction, table of Moore Machine is created

25 Reduction of compatible states for Moore Machine x1x0x1x0 00011110Z S S1S1 S1S1 S2S2 --0 S2S2 S4S4 S2S2 S3S3 -0 S3S3 -S2S2 S3S3 -0 S4S4 S4S4 --S5S5 1 S5S5 S1S1 --S5S5 0 For Moore Machine compatible are states S 1 and S 5 as well as S 2 and S 3. These states have consistent outputs. x1x0x1x0 00011110Z S S 1, S 5 S1S1 S2S2 -S5S5 0 S 2, S 3 S4S4 S2S2 S3S3 -0 S4S4 S4S4 --S5S5 1 After reduction, we get Moore Machine table.

26 Reduction of compatible states of Mealy Machine x1x0x1x0 00011110 S S1S1 S1S1 S2S2 -- S2S2 S4S4 S2S2 S3S3 - S3S3 -S2S2 S3S3 - S4S4 S4S4 --S5S5 S5S5 S1S1 --S5S5 x1x0x1x0 00011110 S S 1, S 3,S 5 S1S1 S2S2 S3S3 S5S5 S 2, S 4 S4S4 S2S2 S3S3 S5S5 SZ S1S1 0 S2S2 0 S3S3 0 S4S4 1 S5S5 0 x1x0x1x0 00011110 S S 1, S 3,S 5 0000 S 2, S 4 1000 State table Output table

27 Encoding Encoding is done for Moore (first) and next for Mealy Machine. x1x0x1x0 00011110Z S 00 a={S 1,S 3, S 5 } abaa0 01b=S 2 cba-0 10c=S 4 c--a1 a b c 0001 11 10

28 Encoded table of Moore Machine x1x0x1x0 00011110Z S 00 a={S 1,S 3, S 5 } abaa0 01b=S 2 11ba-0 c-- - - 10c=S 4 c--a1 x1x0x1x0 00011110Z Q1Q0Q1Q0 00 0100 0 01110100-0 1110-- - - --001

29 Transition Function of Moore Machine x1x0x1x0 00011110 q 1 (t)q 0 (t) 000000 01100- 111-- - 101--0 x1x0x1x0 00011110 q 1 (t)q 0 (t) 000100 01110- 110-- - 100--0 q 1 (t+1) q 0 (t+1)

30 Output function of Moore Machine q 1 (t)q 0 (t)Z 000 010 11- 101

31 Realization with logic gates Simulation: przyklad002.msm

32 Realisation using type sr asynchronous FFs. We will use asynchronous sr FF, that has the following transition table. q(t)  q(t+1) sr 000- 0110 1001 11-0

33 SR FF has two inputs for which we have to find corresponding inputs, using transition table of the FF x1x0x1x0 00011110 q 1 (t)q 0 (t) 0 0000 0 1100- 1 1--- 1 01--0 Q 1 (t+1) q(t)  q(t+1) sr 000- 0110 1001 11-0 x1x0x1x0 00011110 q 1 (t)q 0 (t) 0 0000 0 1100- 1 ---- 1 0---0 s 1 (t+1) x1x0x1x0 00011110 q 1 (t)q 0 (t) 0 ---- 0 10--- 1 0--- 1 00--1 r 1 (t+1)

34 q 0 (t+1) q(t)  q(t+1) sr 000- 0110 1001 11-0 x1x0x1x0 00011110 q 1 (t)q 0 (t) 0 0100 0 1--0- 1 0--- 1 00--0 s 0 (t+1) x1x0x1x0 00011110 q 1 (t)q 0 (t) 0 -0-- 0 1001- 1 1--- 1 0---- r 0 (t+1) x1x0x1x0 00011110 q 1 (t)q 0 (t) 000100 01110- 110-- - 100--0

35 Realisation using asynchronous SR FR. Simulation:przyklad003.msm

36 Solution for Mealy Machine x1x0x1x0 00011110 S S 1, S 3,S 5 S1S1 S2S2 S3S3 S5S5 S 2, S 4 S4S4 S2S2 S3S3 S5S5 x1x0x1x0 00011110 S S 1, S 3,S 5 0000 S 2, S 4 1000 State Table Output table

37 Encoded Mealy Machine Table x1x0x1x0 00011110 S S 1, S 3,S 5 0S1S1 S2S2 S3S3 S5S5 S 2, S 4 1S4S4 S2S2 S3S3 S5S5 x1x0x1x0 00011110 q(t) 00100 11100

38 Transition and output functions of Mealy Machine x1x0x1x0 00011110 q(t) 00100 11100 q(t+1) x1x0x1x0 00011110 q(t) 00000 11000 State table Output tableZ

39 Realization using logic gates Simulation:przyklad005.msm

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