1. 1 Cross ID Tag identification emulator Final presentation Performed by: Shuki Yasharzada Raanan Steinberg Yido Shalev Project instructor: Yossi Hipsh Technion – Israel Institute of Technology Department of Electrical Engineering High Speed Digital Systems Lab

2. 2 Overview Electromagnetic tracking and identifying system. Optional applications: –Electromagnetic bar-code –Blind aid devices. –Information security.

3. 3 Overview Transmitter Product Receiver

4. 4 Project Goals Design and realization of a digital emulator which Identifies Cross ID tag units. The emulator will operate in base band. Realization will be implemented by high speed digital elements.

5. 5 Progress Learning the problem. General design. Equipment learning process Block diagram: –Choosing components. –ID gate realization.

6. 6 `` ID gate test High speed Pulse generator T = 100trise DIP switch Manually controlling delay unit SCOPE trigger

7. 7 `` Block diagram And gate #2 Delay unit Processor + Control unit High speed Pulse generator T = 100 t rise Tags A/D display D 2 = T*G T G E nable E Pulse P Gate Pulse Tag Pulses D1=P*ED1=P*E ∫ D 2 {t 0 + 100T } t0t0 dt Latch Set R Reset S R Int. clock T (Int.) ≈ 10T Main transmitter Tag ID unit LAB-VIEW And gate #1 V out

8. 8 System characterization System characterization Pulse Generator Delay unit And unit Lab-VIEW

9. 9 Pulse Generator Pulse generator 33250A Agilent Pulse width 8 ns Rise time 5 ns Output Trigger

10. 10 System characterization System characterization Pulse Generator Delay unit And unit Lab-VIEW

11. 11 Monolithic 8bit programmable delay line (3D7408-0.25) Min delay 10-14 ns Max delay 77.75 ns 0.25 ns step Delay unit

12. 12 System characterization System characterization Pulse Generator Delay unit And unit Lab-VIEW

13. 13 And Unit

14. 14 System characterization System characterization Pulse Generator Delay unit And unit Lab-VIEW

15. 15 Controller block diagram 8 digital outputs (delay unit control) display LAB-VIEW Controller + Processor Analog input (from the integrator) Digital output (enable for pulse generator)

16. 16 LAB-VIEW Graphical programming language

17. 17 System characterization System characterization Pulse Generator Delay unit And unit Lab-VIEW

18. 18 Identification test Can we recognize the tag pulse? What is the pulse width (Tag*Gate)? What is the pulse rise and fall time? What is the delay (ref and T*G)? Can we determine the Tag delay number?

19. 19 Agilent 33250A pulser Delay Agilent scope 54246A And unit G.P T.P EN '1' Gate unit Tag unit REF T*G*EN 3.1m 0.4m 1m 2.5m 1m 1m

20. 20 Tag emulator block diagram מקור פולסים משהה נשלט (בר-תכנות) פיצול פולס המקור לשלושה פולסים זהים משהה נשלט (בר-תכנות) אוסף מתגים פולס מושהה פולס ייחוס המשמש לכיול תג-הזיהוי פולס מושהה משהה נשלט (בר-תכנות)

21. 21 Tag emulator realization 33250A 80MHz Pulse Generator Low Voltage 1:10 CMOS Clock Driver - MPC946 3 DIP Switches פולס מושהה 3D7408-0.25 שם היצרן : Agilent שם היצרן : MOTOROLA SEMICONDUCTOR שם היצרן : data delay device פולס מושהה פולס ייחוס המשמש לכיול תג-הזיהוי 3D7408-0.25 פולס מושהה

22. 22 Agilent scope 54246A T.P REF 3.1m 1m 2.5m 1m 0.4m Distribution Buffer Mpc 946 Agilent 33250A Pulse generator And unit G.P EN '1' T*G*EN 1m controller 3D7408 Delay Unit DIP SWITCH 3D7408 Delay Unit DIP SWITCH 3D7408 Delay Unit DIP SWITCH 3D7408 Delay Unit DIP SWITCH Distribution Buffer Mpc 946 integrator MC10ELT22 MC10EL04 Gate unit Tag unit

23. 23

24. 24 T*G delay REF T*G

25. 25 T*G pulse width

26. 26 Final experiment Checking every line individually. Finding the reference pulse. Identifying the tag number.

27. 27 Search and identification Gate unit Tag unit G*T No overlap

28. 28 Gate unit Tag unit G*T Partial overlap Search and identification

29. 29 Search and identification Gate unit Tag unit G*T Partial overlap

30. 30 Search and identification Gate unit Tag unit G*T Full overlap

31. 31 Search and identification Gate unit Tag unit G*T Partial overlap

32. 32 Gate unit Tag unit G*T Partial overlap Search and identification

33. 33 Search and identification Gate unit Tag unit G*T No overlap

34. 34 No overlap

35. 35 Full overlap gate unit = 36 ns

36. 36 Partial overlap

37. 37 Tag unit name =14 ns

38. 38 Full overlap gate unit = 50 ns

39. 39 Results We have certain identification of the Tag pulse! We have certain determination of Tag number! T*G pulse width 10.4 ns. T*G rise time 680 ps and fall time 840 ps.

40. 40 Project summary The system can detect the tag. The system can be controlled automatically by an external controller/computer.

41. 41 The End

42. 42 Delay Summary Appendix Delay Summary

43. 43 And unit

44. 44 Electrical scheme for the tag emulator (1) Pulse Generator (IN) 1 3D7408-0.25 15 (OUT) V cc 3.3v 10KΩ V cc 3.3v Pulse in SMA Pulse out V cc 3.3v (IN) 1 3D7408-0.25 15 (OUT) Pulse out 10KΩ 100Ω RFI - Filter V cc 3.3v Test points (IN) 1 3D7408-0.25 15 (OUT) Connections map for the MPC946 9V DC

45. 45 DIP switch #n Output Qa1 from MPC946 10KΩ 9V DC RFI - Filter V cc 5v "1" 10KΩ 1KΩ SMA "1" 3D7408-0.25 Electrical scheme for the tag emulator (2) Connections map for the 3D7408-0.25