1. Recap

2. Instruction Set Architecture (ISA)
The ISA is the interface between hardware and software.
The ISA serves as an abstraction layer between the HW and SW
Software doesn’t need to know how the processor is implemented
Any processor that implements the ISA appears equivalent
An ISA enables processor innovation without changing software
This is how Intel has made billions of dollars.
Before ISAs, software was re-written/re-compiled for each new machine.
Software
Proc #1
ISA
Proc #2

3. What is instruction set architecture (ISA)?
Instruction set of a computer: the portion of the computer visible to the assembly level programmer or to the compiler writer ISA
Defines registers
Defines data transfer modes (instructions) between registers, memory and I/O
There should be sufficient instructions to efficiently translate any program
Next, define instruction set format – binary representation used by the hardware
Variable-length vs. fixed-length instructions

4. Growth/Variations of Processors

5. Instruction Set Architectures
There are 4 classes of ISA
Stack
Embedded processors
Accumulator
Register-memory
Pentium
Register-Register (Load-store)
Sparc

6. Instruction Set Architecture
For a general purpose high-performance computer
Register-Register (Load-store) is the preferred choice
CPI uniform for most instructions
Better pipelining
Fixed length instructions
Simpler encoding
The complier is more complicated

7. Important issues to consider for designing an ISA
What are the different addressing modes that should be used
What is the length of instructions
What are the different instructions used
What is the type and size of operands

8. Addressing Modes Addressing mode Example Meaning Register Add R4,R3
R4  R4+R3
Immediate
Add R4,#3
R4  R4+3
Displacement
Add R4,100(R1)
R4  R4+Mem[100+R1]
Register indirect
Add R4,(R1)
R4  R4+Mem[R1]
Indexed / Base
Add R3,(R1+R2)
R3  R3+Mem[R1+R2]
Direct or absolute
Add R1,(1001)
R1  R1+Mem[1001]
Memory indirect
Add
R1  R1+Mem[Mem[R3]]
Auto-increment
Add R1,(R2)+
R1  R1+Mem[R2]; R2  R2+d
Auto-decrement
Add R1,–(R2)
R2  R2-d; R1  R1+Mem[R2]
Scaled
Add R1,100(R2)[R3]
R1  R1+Mem[100+R2+R3*d]

9. 85%
75%

10. Addressing Modes Register (direct) mode Example: ADD $r1, $r2, $r3
op: opcode
rs: first source register
rt: second source register
rd: destination register op rs rt rd
register
Example: ADD $r1, $r2, $r3 op 1 2 3
100
$r1 = 100

11. Addressing Modes Immediate mode Example: ADDI $r3, $r1, 12 op: opcode
rs: source register
rt: destination register
immed: constant op rs rt
immed
Example: ADDI $r3, $r1, 12 op 3 1 12

12. Addressing Modes Displacement mode + Example: LOAD $r1, 100($r2) + oprs rt
immed
register
Memory +
Example: LOAD $r1, 100($r2) op 2 1
100
150
Memory 88 +
Address = 250
$r2 = 150; 100($r2) = 88

13. Displacement and Immediate Values
Important addressing modes: Register, immediate, displacement, register indirect. Account for 88% of workload.
Through measurements, bits are enough to cover the majority of cases for the value of immediate
This will allow to have instruction sets of fixed size of 32 bits – most microprocessors
opcode rs rt 6 5 rd
shamt
func
R-Type Format
opcode rs rt
immediate 6 5 16
I-Type Format
opcode
immediate 6 26
J-Type Format

14. Instruction Usage Example: Top 10 Intel X86 Instructions
Rank
instruction
load
conditional branch
compare
store
add
and
sub
move register-register
call
return
Total
Integer Average Percent total executed 1
22%
20%
16%
12% 8% 6% 5% 4% 1%
96% 2 3 4 5 6 7 8 9 10
Observation: Simple instructions dominate instruction usage frequency.

15. Instruction Set Encoding
Considerations affecting instruction set encoding:
To have as many registers and address modes as possible.
The Impact of the size of the register and addressing mode fields on the average instruction size and on the average program.
To encode instructions into lengths that will be easy to handle in the implementation. On a minimum to be a multiple of bytes.

16. Instruction Format Fixed Variable Hybrid Summary:
Operation, address specifier 1, address specifier 2, address specifier 3.
MIPS, SPARC, Power PC.
Variable
Operation & # of operands, address specifier1, …, specifier n.
VAX
Hybrid
Intel x86
operation, address specifier, address field.
Operation, address specifier 1, address specifier 2, address field.
Operation, address field, address specifier 1, address specifier 2.
Summary:
If code size is most important, use variable format.
If performance is most important, use fixed format.

17. Three Examples of Instruction Set Encoding
Operations &
no of operands
Address
specifier 1
Address
field 1
Address
specifier n
Address
field n
Variable: VAX (1-53 bytes)
Operation
Address
field 1
Address
field 2
Address
field3
Fixed: DLX, MIPS, PowerPC, SPARC
Operation
Address
field
Address
Specifier
Address
Specifier 1
Address
Specifier 2
Operation
Address field
Address
Specifier
Address
field 2
Operation
Address
field 1
Hybrid : IBM 360/370, Intel 80x86

18. Summary: ISA
Use general purpose registers with a load-store architecture.
Support these addressing modes: displacement, immediate, register indirect.
Support these simple instructions: load, store, add, subtract, move register, shift, compare equal, compare not equal, branch, jump, call, return.
Support these data size: 8-,16-,32-bit integer, IEEE FP standard.
Provide at least 16 general purpose registers plus separate FP registers and aim for a minimal instruction set.

19. Alternative Architectures
Design alternative:
provide more powerful operations
goal is to reduce number of instructions executed
danger is a slower cycle time and/or a higher CPI
Let’s look (briefly) at IA-32
“The path toward operation complexity is thus fraught with peril. To avoid these problems, designers have moved toward simpler instructions”

20. IA - 32 1978: The Intel 8086 is announced (16 bit architecture)
1980: The 8087 floating point coprocessor is added
1982: The increases address space to 24 bits, +instructions
1985: The extends to 32 bits, new addressing modes
: The 80486, Pentium, Pentium Pro add a few instructions (mostly designed for higher performance)
1997: 57 new “MMX” instructions are added, Pentium II
1999: The Pentium III added another 70 instructions (SSE)
2001: Another 144 instructions (SSE2)
2003: AMD extends the architecture to increase address space to 64 bits, widens all registers to 64 bits and other changes (AMD64)
2004: Intel capitulates and embraces AMD64 (calls it EM64T) and adds more media extensions
“This history illustrates the impact of the “golden handcuffs” of compatibility:
“adding new features as someone might add clothing to a packed bag” “an architecture that is difficult to explain and impossible to love”

21. IA-32 Overview Complexity: Instructions from 1 to 17 bytes long
one operand must act as both a source and destination
one operand can come from memory
complex addressing modes e.g., “base or scaled index with 8 or 32 bit displacement”
Saving grace:
the most frequently used instructions are not too difficult to build
compilers avoid the portions of the architecture that are slow
“what the 80x86 lacks in style is made up in quantity, making it beautiful from the right perspective”