1. Cyclic Combinational Circuits and Other Novel Constructs Marc D. Riedel California Institute of Technology Marrella splendensCyclic circuit (500 million year old Trilobite)(novel construct)

2. inputsoutputs The current outputs depend only on the current inputs. Combinational Circuits combinational logic

3. NAND OR AND NOR 1 0 0 1 1 1 1 0 1 0 0 1 Acyclic (i.e., feed-forward) circuits are always combinational. Combinational Circuits

4. Acyclic (i.e., feed-forward) circuits are always combinational. Are combinational circuits always acyclic? “Combinational networks can never have feedback loops.” “A combinational circuit is a directed acyclic graph (DAG)...” Combinational Circuits 1 0 0 1 1 1 NAND OR AND NOR 1 0 1 0 0 1

5. Acyclic (i.e., feed-forward) circuits are always combinational. Are combinational circuits always acyclic? “Combinational networks can never have feedback loops.” “A combinational circuit is a directed acyclic graph (DAG)...” Combinational Circuits Designers and EDA tools follow this practice.

6. Circuits with Cycles a b x c d x AND OR AND OR )))((( 1 fxcdxab 1 f 

7. x 0 0 0 a b c d AND OR AND OR x x 0 )))((( 1 fcdxab 1 f  0 Circuits with Cycles

8. x x x 0 0 a b c d AND OR AND OR 0 )))((( 1 fxcdab 1 f  Circuits with Cycles

9. x 1 x 1 x x a b c d AND OR AND OR 1 1 1 )))((( 1 fcdab 1 f  Circuits with Cycles

10. 1 1 x x x a b c d AND OR AND OR 1 ))((cdab 1 f  )( 2 abxcdf  Circuit is cyclic yet combinational; computes functions f 1 and f 2 with 6 gates. An acyclic circuit computing these functions requires 8 gates. Circuits with Cycles

11. A cyclic topology permits greater overlap in the computation of the two functions: x x a b c d AND OR AND OR There is no feedback in a functional sense. Circuit is cyclic yet combinational; computes functions f 1 and f 2 with 6 gates. An acyclic circuit computing these functions requires 8 gates. )( 2 abxcdf  Circuits with Cycles x))((cdab 1 f 

12. Prior Work (early era) Kautz and Huffman discussed the concept of feedback in logic circuits (in 1970 and 1971, respectively). McCaw and Rivest presented simple examples (in 1963 and 1977, respectively).

13. Prior Work (later era) Stok observed that designers sometimes introduce cycles among functional units (in 1992). Malik, Shiple and Du et al. proposed techniques for analyzing such circuits (in 1994,1996, and 1998 respectively).

14. Cyclic Circuits: Key Contributions Practice Theory Devised efficient techniques for analysis and synthesis. Formulated a precise model for analysis. Implemented the ideas and demonstrated they are applicable for a wide range of circuits. Provided constructions and lower bounds proving that cyclic designs can be more compact.

15. Outline of Talk Analysis: circuit model, symbolic techniques. Synthesis: framework, implementation, and results. Theory: circuit complexity (limited). Application of circuit design techniques to biological systems. Current & Future Research Directions Cyclic Circuits

16. Fixed-point analysis over a ternary-valued (0, 1, ?) domain. Regardless of the prior values. Independently of all timing assumptions. Circuit Model A circuit must produces definite output values for each input combination (in the “care” set): A sequence of controlling values always determines the output. Formally: Informally:

17. Controlling Values a “controlling” input full set of “non-controlling” inputs unknown/undefined output 0 ? 0 AND 1 1 1 1 ? ?

18. Each gate has delay in [ 0, t d ] The arrival time at a gate output is determined: either by the earliest controlling input; AND 1313 0202 0606 0303 Timing Model arrival times (Assume t d = 1 )

19. The arrival time at a gate output is determined: either by the earliest controlling input; AND 1313 1212 1616 or by the latest non-controlling input. 1717 Timing Model Each gate has delay in [ 0, t d ] (Assume t d = 1 ) 1313 0202 0606 0303

20. Analysis Functional Analysis: determine what is computed. Timing Analysis: determine how long it takes to compute it. level: l 1 = 1 l 2 = 1 l 3 = 2 l 5 = 2 l 4 = 3 a b a b g1g1 g2g2 g3g3 g4g4 g5g5 c c 1010 1010 1010 1010 1010 1212 0202 1212 1 0101 1010

21. Analysis Explicit analysis: ORAND Functional Analysis: determine what is computed. Timing Analysis: determine how long it takes to compute it.

22. ORAND 000 0101 0202 0101 Analysis000 0101 0202 0101 Explicit analysis: Functional Analysis: determine what is computed. Timing Analysis: determine how long it takes to compute it.

23. 0202 000 0101 0202 0101 ORAND 0 10100 0101 0303 m inputs explict evaluation intractable  combinations; Analysis000 0101 0202 0101 00 1010 0101 0202 0303 Explicit analysis: Functional Analysis: determine what is computed. Timing Analysis: determine how long it takes to compute it.

24. ORAND Analysis 0 0202 10100 0101 0303 Symbolic analysis: binary, multi-terminal decision diagrams. (See “Timing Analysis of Cyclic Circuits,” IWLS, ’04) 0 1 0101 0202 ? 1313 Functional Analysis: determine what is computed. Timing Analysis: determine how long it takes to compute it.

25. Synthesis General methodology: optimize by introducing feedback in the substitution/minimization phase. Developed a tool called CYCLIFY within Berkeley SIS Environment. Optimizations are significant and applicable to a wide range of circuits. Design a circuit to meet a specification.

26. Example: 7 Segment Display Inputs a b c d e f g Output 1001 0001 1110 0110 1010 0010 1100 0100 1000 0000 0123 xxxx 9 8 7 6 5 4 3 2 1 0

27. Example: 7 Segment Display a b c d e f g Output

28. Substitution Basic minimization/restructuring operation: express a function in terms of other functions. Substitute b into a: (cost 9) a  ))(( 302321320 xxxxxxxxx  (cost 8) Substitute c into a: (cost 5) Substitute c, d into a: (cost 4) a  )( 323212 bxxxxxbx  a  cxxcx 321  a  dccx  1

29. Substitution/Minimization Berkeley SIS Tool a  ))(( 302321320 xxxxxxxxx  },,,{fdcb target function substitutional set a  dccx  1 low-cost expression   

30. Acyclic Substitution g f e b a c d Select an acyclic topological ordering: g f e d c b a       

31. g f d c b a       edcaxx  21 dccx  1 xxxxxxxxx  102213321 ))((dxxxxxx  102320 )(cdxx  10 )( Select an acyclic topological ordering: Area (literal count): 37 Acyclic Substitution e   3 cxb d ba  f

32. Select an acyclic topological ordering: Nodes at the top benefit little from substitution. g f d c b a       edcaxx  21 dccx  1 xxxxxxxxx  102213321 ))((dxxxxxx  102320 )(cdxx  10 )( e   3 cxb d ba  f

33. Cyclic Substitution How can we find a cyclic solution that is combinational? g f d c b a       e  ?

34. Target Candidates Simpler Example: Cyclic Substitution

35. Target Candidates Simpler Example: Cyclic Substitution

36. Target Candidates Simpler Example: Cyclic Substitution

37. “Break-Down” approach Search performed outside space of combinational solutions. Terminates on optimal solution * cost 12 cost 13 cost 12 cost 13 combinational cost 14 Branch and Bound

38. “Build-Up” approach cost 17 cost 16 cost 15 not combinational cost 14 Branch ( without Bounding ) cost 13 best solution Search performed inside space of combinational solutions

39. g f e d c b a        Area (literal count): 34 Combinational solution: xe 0 bxa 3  gxxxax 1023 )(  axxex 321 )(  exxxxxx 312320 )(  cxxcx 301  xxxfx 1023 )(  f Example: 7 Segment Display

40. Limit the density of edges a priori Limit breadth Tunnel depth-wise (with backtracking) Branch and Bound Heuristics: for target functions, configurations n Large search space: (See “The Synthesis of Cyclic Circuits,” DAC, ’03)

41. Optimization for Area Number of NAND2/NOR2 gates for Berkeley SIS vs. CYCLIFYsolutions BenchmarkBerkeley SISCYCLIFYImprovement 5xp120318210.34% ex619415221.65% planet9438895.73% s3862312223.90% bw30225515.56% cse3443294.36% pma4093933.91% s5105144836.03% duke284767320.54% styr85875811.66% s1488108410037.47% Based on “script.rugged” sequence and technology mapping.

42. Optimization for Area and Delay Berkeley SISCYCLIFY benchmarkAreaDelayAreaImprovementDelayImprovement p82175191674.57%1521.05% t1343173274.66%1417.65% in3599405931.00%3317.50% in2590345585.42%2914.71% 5xp12102318014.29%224.35% bw280282549.29%2028.57% s510452284441.77%2414.29% s1566365424.24%3113.89% duke2742387163.50%3410.53% s14881016439952.07%3420.93% s149410904610791.01%3915.22% Number of NAND2/NOR2 gates and the Delay of Berkeley SIS vs. CYCLIFY solutions Based on “script.delay” sequence and technology mapping.

43. Practice Improvements in area (and consequently power) and delay are significant. Similar improvements were obtained for larger scale circuits: e.g., the ALU of an 8051 microprocessor. E.D.A. companies (Altera and Synopsys) have expressed strong interest.

44. Theory Prove that cyclic implementations can have fewer gates than equivalent acyclic ones. cyclic circuit acyclic circuit (optimal) functions, n variables, m fan-in gates d gates n more than gates n

45. 6/7 Construction Cyclic Circuit: 6 functions, 3 variables, 6 fan-in 2 gates. ANDORANDORANDOR Acyclic Circuit: at least 7 fan-in 2 gates.

46. f1f1 f2f2 f3f3 f4f4 f5f5 f6f6

47. Theory Exhibit a cyclic circuit that is optimal in terms of the number of gates, say with C(n) gates, for n variables. Prove a lower bound on the size of an acyclic circuit implementing the same functions, say A(n) gates. Strategy: Main Result:

48. Current & Future Research Interests Logic Synthesis and Verification: functional decomposition, symbolic data structures, cyclic decision diagrams. Novel Platforms: asynchronous models, nanotechnology, noisy/probabilistic gates. Computational Biology analysis of intracellular biochemical networks.