1. 1 Pertemuan 15 Organisasi I/O: I Matakuliah: T0324 / Arsitektur dan Organisasi Komputer Tahun: 2005 Versi: 1

2. 2 Learning Outcomes Pada akhir pertemuan ini, diharapkan mahasiswa akan mampu : Mahasiswa dapat membandingkan beberapa metode pengaksesan peralatan I/O dalam sistem komputer ( C4 ) ( No TIK : 7 )

3. 3 Chapter 4. Input/Output Organization: I

4. 4 ProcessorMemory I/O device 1I/O devicen Bus Figure 4.1. A single-bus structure.

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7. 7 Move#LINE,R0Initializememorypointer. WAITKTestBit#0,STATUSTestSIN. Branch=0WAITKWaitforcharactertobeentered. MoveDATAIN,R1Readcharacter. WAITDTestBit#1,STATUSTestSOUT. Branch=0WAITDWaitfordisplaytobecomeready. MoveR1,DATAOUTSendcharactertodisplay. MoveR1,(R0)+Storecharacterandadvancepointer. Compare#$0D,R1CheckifCarriageReturn. Branch 00 WAITKIfnot,getanothercharacter. Move#$0A,DATAOUTOtherwise,sendLineFeed. CallPROCESSCallasubroutinetoprocess theinputline. Figure 4.4 A program that reads one line from the keyboard stores it in memory buffer, and echoes it back to the display.

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9. 9 Processor INTR R Figure 4.6.An equivalent circuit for an open-drain bus used to implement a common interrupt-request line. INTR1INTR2INTRn V dd INTR

10. 10 Figure 4.7. Implementation of interrupt priority using individual interrupt-request and acknowledge lines.

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12. 12 MainProgram Move#LINE,PNTRInitializebufferpointer. ClearEOLClearend-of-lineindicator. BitSet#2,CONTROLEnablekeyboardinterrupts. BitSet#9,PSSetinterrupt-enablebitinthePS.... Interrupt-serviceroutine READMoveMultipleR0-R1,(SP)SaveregistersR0andR1onstack. MovePNTR,R0Loadaddresspointer. MoveByteDATAIN,R1Getinputcharacterand MoveByteR1,(R0)+storeitinmemory. MoveR0,PNTRUpdatepointer. CompareByte#$0D,R1CheckifCarriageReturn. Branch 00 RTRN Move#1,EOLIndicateendofline. BitClear#2,CONTROLDisablekeyboardinterrupts. RTRNMoveMultiple(SP)+,R0-R1RestoreregistersR0andR1. Return-from-interrupt Figure 4.9. Using interrupts to read a line of characters from a keyboard via the registers in Figure 4.3. –

13. 13 OSINITSetinterruptvectors: Time-sliceclockSCHEDULER SoftwareinterruptOSSERVICES KeyboardinterruptsIOData... OSSERVICESExaminestacktodeterminerequestedoperation. Callappropriateroutine. SCHEDULERSaveprogramstate. Selectarunnableprocess. Restoresavedcontextofnewprocess. PushnewvaluesforPSandPConstack. Returnfrominterrupt. (a) OS initialization, services, and scheduler IOINITSetprocessstatustoBlocked. Initializememorybufferaddresspointerandcounter. Calldevicedrivertoinitializedevice andenableinterruptsinthedeviceinterface. Returnfromsubroutine. IODATAPolldevicestodeterminesourceofinterrupt. Callappropriatedriver. IfEND=1,thensetprocessstatustoRunnable. Returnfrominterrupt. (b) I/O routines KBDINITEnableinterrupts. Returnfromsubroutine. KBDDATACheckdevicestatus. Ifready,thentransfercharacter. Ifcharacter=CR,then{setEND=1;Disableinterrupts } elsesetEND=0. Returnfromsubroutine. (c) Keyboard driver Figure 4.10. A few operating system routines.   

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16. 16 Mainprogram MOVR0,#0 STRR0,EOLClearEOLflag. ADRR1,DATAINLoadaddressofRegisterDATAIN. LDRBR0,[R1,#3]Get contentsofCONTROLregister. ORRR0,R0,#4SetbitKENinregisterCONTROL STRBR0,[R1,#3]toenablekeyboardinterrupts. MOVR0,#&50EnableIRQinterruptsinprocessor MSRCPSR,R0andswitchtousermode.... IR Q Interrupt-serviceroutine READSTMFDR13!,{ R0  R2,R14 irq}SaveR0,R1,andR14irqonthestack. ADRR1,DATAINLoadaddressof register DATAIN. LDRBR0,[R1]Getinputcharacter. LDRR2,PNTRLoadpointervalue. STRBR0,[R2],#1Storecharacterandincrementpointer. STRR2,PNTRUpdatepointervalueinthememory. CMPBR0,#&0DCheckifCarriageReturn. LDMNEFDR13!,{ R0  R2,R14 irq}Ifnot,restoreregisters SUBNESPC,R14irq,#4andreturn. LDRB R0,[R1,#3] OtherwisegetCONTROLregister. ANDR0,R0,#&FBClearbitKEN STRBR0,[R1,#3]todisablekeyboardinterrupts. MOVR0,#1SetEOLflag. STRR0,EOL LDMFDR13!,{R0-R2,R14}Restoreregisters SUBSPC,R14irq,#4andreturn. Figure 4.13. An ARM interrupt-service routine to read an input line from a keyboard based on Figure 4.9.

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18. 18 Mainprogram MOVE.L#LINE,PNTRInitializebufferpointer. CLREOLClearend-of-lineindicator. ORI.B#4,CONTROLSetbitKEN. MOVE#$100,SRSetprocessorpriorityto1.... Interrupt-serviceroutine READMOVEM.LA0/D0,(A7)SaveregistersA0,D0onstack. MOVEA.LPNTR,A0Loadaddresspointer. MOVE.BDATAIN,D0Getinputcharacter. MOVE.BD0,(A0)+Storeitinmemorybuffer. MOVE.LA0,PNTRUpdatepointer. CMPI.B#$0D,D0CheckifCarriageReturn. BNERTRN MOVE#1,EOLIndicateendofline. ANDI.B#$FB,CONTROLClearbitKEN. RTRNMOVEM.L(A7)+,A0/D0RestoreregistersD0,A0. RTE Figure 4.15. A 68000 interrupt-service routine to read an input line from a keyboard based on Figure 4.9. –

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20. 20 Mainprogram MOVEOL,0 MOVBL,4 ORCONTROL,BLSetKENtoenablekeyboardinterrupts. STISetinterruptflaginprocessorregister.... Interrupt-serviceroutine READPUSHEAXSaveregisterEAXonstack. PUSHEBXSaveregisterEBXonstack. MOVEAX,PNTRLoadaddresspointer. MOVBL,DATAINGetinputcharacter. MOV[EAX],BLStorecharacter. INCDWORDPTR[EAX]IncrementPNTR. CMPBL,0DHCheckifcharacterisCR. JNERTRN MOVBL,4 XORCONTROL,BLClearbitKEN. MOVEOL,1SetEOLflag. RTRNPOPEBXRestoreregisterEBX. POPEAXRestoreregisterEAX. IRET Figure 4.17. An interrupt-servicing routine to read one line from a keyboard using interrupts on IA-32 processors.

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22. 22 Figure 4.19. Use of DMA controllers in a computer system.

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24. 24 Figure 4.21. Sequence of signals during transfer of bus mastership for the devices in Figure 4.20.

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26. 26 Pertemuan 16 Organisasi I/O: II Matakuliah: T0324 / Arsitektur dan Organisasi Komputer Tahun: 2005 Versi: 1

27. 27 Learning Outcomes Pada akhir pertemuan ini, diharapkan mahasiswa akan mampu : Membandingkan beberapa metode pengaksesan peralatan I/O dalam sistem komputer ( C4 ) ( No TIK : 7 )

28. 28 Chapter 4. Input/Output Organization: II

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39. 39 DATAIN 1 SIN Ready A31 A1 A0 Address decoder D7 D0 R/W Figure 4.33. Combined input/output interface circuit. A2 DATAOUT Input status Bus PA7 PA0 CA PB7 PB0 CB1 CB2 SOUT D1 RS1 RS0 My-address Handshake control Master- Ready Slave-

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41. 41 Handshake control DATAOUT Printer data Idle Valid Read Load SOUT ready A31 A1 A0 Address decoder D 7 Q 7 D 0 Q 0 D7 D0 Figure 4.35.A parallel point interface for the bus of Figure 4.25, with a state-diagram for the timing logic. statusdata D 1 Q 1 D0 Timing Logic Clock My-address R/W Slave- Idle Respond My-address Go Go=1

42. 42 Figure 4.36.Timing for the output interface in Figure 4.35. 123 Clock Address R/W Data Slave-ready Go Time

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44. 44 memory Processor Bridge Processor bus PCI bus Main memory Additional controller CD-ROM controller Disk Disk 1Disk 2 ROM CD- SCSI controller USB controller Video KeyboardGame disk IDE SCSI bus Figure 4.38. An example of a computer system using different interface standards. ISA interface Ethernet interface

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48. 48 FreeArbitrationSelection Targets examine ID DB2 DB5 DB6 BSY SEL Figure 4.42.Arbitration and selection on the SCSI bus. Device 6 wins arbitration and selects device2.

49. 49 Host computer Root hub Hub Figure 4.43. Universal Serial Bus tree structure. I/O device Hub I/O device I/O device Hub I/O device I/O device I/O device

50. 50 Host computer Root Hub Hub A Device Figure 4.44. Split bus operation D F/LS HS - High speed F/LS- Full/Low speed Hub B Device C

51. 51 PID 0 1 2 3 0 0 1 2 3 (a) Packet identifier field PIDADDRENDPCRC16 8745Bits (b) Token packet, IN or OUT PIDDATACRC16 80 to 819216Bits (c) Data packet Figure 4.45. USB packet format.

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53. 53 PIDFrame numberCRC5 8115Bits (a) SOF Packet Figure 4.47. USB frames. ST3DS 1-ms frame T7DT3D S- Start-of-frame packet Tn- Token packet, address = n D- Data packet A- ACK packet (b) Frame example

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55. 55 Table 4.1. Interrupt vector addresses for ARM processor AddressExceptionModeentered (hex) 0ResetSupervisor 4UndefinedinstructionUndefined 8SoftwareinterruptSupervisor CAbortduringprefetchAbort 10AbortduringdataAbort 14Reserved 18IRQ Q 1CFIQ

56. 56 Table 4.2. Address correction during return from exception. ExceptionSavedaddress*DesiredReturninstruction returnaddress UndefinedinstructionPC+4 MOVSPC,R14und SoftwareinterruptPC+4 MOVSPC,R14svc PrefetchAbortPC+4PCSUBSPC,R14abt,#4 DataAbortPC+8PCSUBSPC,R14abt,#8 IRQPC+4PCSUBSPC,R14irq,#4 FIQPC+4PCSUBSPC,R14fiq,#4 *PCistheaddressoftheinstructionthatcausedtheexception.ForIRQandFIQ, itistheaddressofthefirstinstructionnotexecutedbecauseoftheinterrupt.

57. 57 Table 4.3. Data transfer signals on the PCI bus. NameFunction CLKA33-MHzor66-MHzclock. FRAME#Sentbytheinitiatortoindicatethedurationofa transaction. AD32address/datalines,whichmaybeoptionally increasedto64. C/BE#4command/byte-enablelines(8fora64-bitbus). IRDY#,TRDY#Initiator-readyandTarget-readysignals. DEVSEL#Aresponsefromthedeviceindicatingthatithas recognizeditsaddressandisreadyforadata transfertransaction. IDSEL#InitializationDeviceSelect.

58. 58 Table 4.4 The SCSI bus signals. CategoryNameFunction DataDB(0)to DB(7) Datalines:Carryonebyteofinformation duringtheinformationtransferphaseand identifydeviceduringarbitration,selectionand reselectionphases DB(P)Paritybitforthedatabus PhaseBSYBusy:Assertedwhenthebusisnotfree SELSelection:Assertedduringselectionand reselection Information type C/DControl/Data:Assertedduringtransferof controlinformation(command,statusor message) MSGMessage:indicatesthattheinformationbeing transferredisamessage HandshakeREQRequest:Assertedbyatargettorequestadata transfercycle A CKAcknowledge:Assertedbytheinitiatorwhenit hascompletedadatatransferoperation Directionof transfer I/OInput/Output:Assertedtoindicateaninput operation(relativ e totheinitiator) Other A TNAttention:Assertedbyaninitiatorwhenit wishestosendamessagetoatarget RSTReset:Causesalldevicecontrolstodisconnect fromthebusandassumetheirstart-upstate – – – – – – – – – – – –