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Application-Specific Hardware Computing Without Processors Mihai Budiu mihaib@cs.cmu.edu October 6, 2001 SOCS-4
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2 Complexity 4004 80286 80386 Pentium Pentium III
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3 A New Approach CPU Compiler Program Executable Reconfigurable hw Configuration Compiler CAD Tool Program
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4 Outline Reconfigurable Hardware Application-Specific Hardware (ASH) ASH Properties Conclusions
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5 Reconfigurable Hardware Universal gates and/or storage elements Interconnection network Programmable switches
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6 Switch controlled by a 1-bit RAM cell 00010001 Universal gate = RAM a0 a1 a0 a1 data a1 & a2 0 data in control Main RH Ingredient: RAM Cell
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7 Place and Route int reverse(int x) { int k,r=0; for (k=0; k<64; k++) r |= x&1; x = x >> 1; r = r << 1; } int func(int* a,int *b) { int j,sum=0; for (j=0; *a>0; j++) sum+=reverse(*b
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8 Application C ProgramVerilog CADCompiler OS support communication manual RH Today
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9 Three Models of Computation CPUASIC Universal Interpretation Custom Direct execution RH Universal Direct execution Defect tolerance
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10 Outline Reconfigurable Hardware Application-Specific Hardware (ASH) ASH Properties Conclusions
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11 Application-Specific Hardware Reconfigurable hardware HLL program Compiler Circuit
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12 CASH: Compiling for ASH Memory partitioning Interconnection net Circuits C Program RH
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13 Stages of Compilation 1. Program int reverse(int x) { int k,r=0; for (k=0; k > 1; r = r << 1; } } Unknown latency ops. Computations & local storage 2. Split-phase Abstract Machines 3. Configurations placed independently 4. Placement on chip
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14 Split-phase Abstract Machines SAM 1 SAM 2 SAM 3 CFG
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15 Hyperblock => SAM Single-entry, multiple exit May contain loops
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16 Computation = Dataflow x = a & 7;... y = x >> 2; Programs & a 7 >> 2 x Circuits variables wires
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17 Speculation if (x > 0) y = -x; else y = b*x; * xb0 y ! ComputationPredicates -> Q
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18 Loops for (i=0; i < 10; i++) a[i] += i; + load + store &a[0] + 1 i 0 a[0] a[1] a[2] a[3] = Pipelining
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19 Example int f(void) { int i=0, j = 0; for (; i < 10; i++) j += i; return j; }
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20 Outline Reconfigurable Hardware Application-Specific Hardware (ASH) ASH Properties Conclusions
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21 Defect Tolerance CPU One defect: chip useless ASH Can reconfigure around defects
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22 Power Consumption CPU 100+W 30M transistors switching @ 2Ghz ASH 1 SAM active, all other idle
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23 Verification CPU Huge effort Extremely complex ASH Program translation validation: feasible program compilerCPU program compiler P in = P out
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24 CAD Tools CPU Lots of exceptions handled manually Very long time ASH Local structures Interactive compilation
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25 Circuit Size circuit # operations All circuits for all programs in SpecINT95 and Mediabench
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26 Total Size (Largest 2 Programs) Benchmarkjpeg_e147.vortex Lines 26,88167,210 SAMs 1,3311,433 FP 153 4 Load/store 8,693 24,913 Call/ret 1,964 9,602 Predicates 8,167 39,195 Arithmetic 1,022,023 1,448,933 Mux 200,354 239,839 Registers 76,722 32,850 UnitsUnits Bit-opsBit-ops
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27 Implications Enough resources in the near future A case for datapath oriented RH: –a better match for computation –high density –fast configuration –more amenable to compilation –few predicate operations
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28 Instruction-Level Parallelism CPU Wide execution path (4-6) Low sustained ILP (~1.5) ASH ILP statically extracted Sustained >3
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29 ILP circuit # avg ILP
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30 Cost CPU Plant = 3B$ Mask = 100K$ (need 20+) Design = ?M$ ASH Can use defective chips Same masks for all chips Design = free
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31 Summary Microprocessor complexity becomes overwhelming Application-Specific Hardware (ASH) translates applications into hardware ASH has novel properties and promises to scale well with increasing resources
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32 Extras CPU + ASH Speculation and critical paths Computing predicates
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33 CPU+ASH core computation support computation + OS + VM CPUASH Memory HLL Program back
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34 Speculation if (x > 0) y = -x; else y = b*x; * x b0 y ! slow ComputationPredicates -> -> and Eager Muxes back to talk back to extras
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35 Computing Predicates Correct for irreducible graphs Correct even when speculatively computed Can be eagerly computed st b back
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