1. Off-chip Decoupling Capacitor Allocation for Chip Package Co-Design Hao Yu Berkeley Design Automationhao.yu@berkeley-da.com Chunta Chu and Lei He EE Department UCLA The work was performed at UCLA and was partially supported by NSF and UC-MICRO

2. 2 Decap Allocation for Clean Power Delivery n Chip-package co-design requires a noise-free off-chip power delivery system (PDS) l Modeling inductance is a must n Decoupling capacitors (decaps) are allocated on chip-package interface to satisfy power integrity n It is a challenging task to find a fast yet accurate decap allocation for a large- scale design How to consider the large and complex physical-level layout during the system- level design? decap cc

3. 3 Physical Level Challenge n Finite parastic impedance affects the circuit functionality at chip-package interface l Supply volatage drop and electromagnetic (EM) coupling n Distributed post-layout model burdens the system-level power integrity analysis and design l Millions of nodes and terminals with dense inductances Module 1 Module 2

4. 4 System Level Challenge System-level synthesis needs to explore the design space composed by those tunable layout parameters Decap allocation: How to select the size? Where to insert? It requires the sensitivity information by perturbing the nominal design parameters Optimization trajectory driven by sensitivity x0x0 x2x2 xnxn … Perturbed design space x1x1 1 2 34 5 6 78

5. 5 The Need of Macromodeling Representing a large and complex power delivery system blindly leads to expensive design cycles A compact representation by macromodeling is needed n Existing decap allocation methods with macromodeling [Zheng:CICC’04, Chen:ISPD’06] l Generate PDS macromodel l Apply simulated annealing to add/remove one decap to a legal position l Can not efficiently handle a large-scale design

6. 6 Limitations of Existing Macromodeling n Macromodeling algorithms [PVL, PACT, PRIMA] are limited to handle a large-scale PDS 1. Become ineffective when terminal number is large 2. Do not provide the sensitivity information 3. Destroy the structure of state matrix Small but dense project How to use it ?

7. 7 Our Decap Problem Formulation n A multiple-ring-based problem formulation l Represent decap solution by combination of multi-level templates l Constrain by noise integral at I/O instead of noise amplitude in [ Chen:ISPD’06 ] n Optimization Method l Each step inserts a template with a given decap type based on sensitivity instead of simulated-annealing The key is to efficiently calculate sensitivity from macromodel

8. 8 TBS2: Macromodeling for PDS n Principle Terminal Selection l Capture the essential input/output behavior n Parameterization l Compute performance sensitivities from the layout modifications n Structured Simulation l Sparsely arrange couplings (sparsity), leverage diverse physical domains (latency) and analyze at block-levels (hierarchy) A structured and parameterized macromodel connects layout with system

9. 9 TBS2 (1) Principle Terminal Selection The input signals ( J =B x I ) are temporally correlated Described by a correlation matrix C (N x N) Correlated terminals [ b 0 b 1 b 2 ] can be simplified with use of a principal component analysis (PCA) n Select K principle terminals by K-means method

10. 10 TBS2 (2) Parameterization Decaps can be parametrically described by The sizing vector ( D ) for M2 types of decaps and the topological matrix ( X ) for M1 levels of rings Total M1XM2 types of parameterized templates described by a parameterized state matrix in s-domain 1 2 34 5 6 78 1 2 3 4 5 6 7 8 1-1 0 0 0 1 0 0 0 X(2,6)=

11. 11 TBS2 (2) Structured Stamping 1. Partition the nominal state matrices according to clustered terminals 2. Triangularize the partitioned state matrices 3. Triangularize the nominal and sensitivity states in each local block 4. Details can be found TBS1[Yu:DAC’06] and [Yu:ISLPED’06]

12. 12 Structured projection Block-wise nominal and sensitivity Sparse and block-triangular TBS2 (3) Structured Macromodeling Details can be found in TBS1 [Yu:DAC’06] and [Yu:ISLPED’06]

13. 13 Improved Accuracy By TBS2 Reduction A non-uniform RLC mesh is reduced by an 80 th -order reduction using TBS2 and PRIMA TBS2 matches more poles than PRIMA w.r.t principle terminals The waveform accuracy is improved in both frequency/time domain by TBS2

14. 14 Our Decap Algorithm Overview 1. Apply TBS2 just one-time to generate a structured and parameterized macromodel 2. Calculate block-level nominal noise at each terminal and its sensitivity w.r.t the partitioned template 3. Check if noise integral satisfies constraints 4. Allocate decaps for each block according to the sensitivity in a greedy fashion TBS2 Check Constraints update Template Calculate nominal+ sensitivity

15. 15 Reduced Runtime and Cost of Decap Allocation Comparing three methods: 1) Simulated-annealing with noise amplitude [Chen:ISPD’06]; 2) Multiple-ring with noise amplitude [this paper]; 3) Multiple-ring with noise integral [this paper] MRA-NI is up to 97X faster than SA-NA due to structured and- parameterized macromodel from TBS2 MRA-NI reduces decap cost by up to 16% due to a more accurate integrity metric using noise integral

16. 16 Conclusions 1. Macromodel connects the system-level design with the physical-level layout 2. TBS2: Structured and parameterized macromodel Provide a fast yet accurate computational prototyping for large/complex system Solve an integrity-driven decap allocation for chip-package co-design Such a block-wise macromodel and optimization can be applied to other layout optimization problems