1. Mic-1: Microarchitecture University of Fribourg, Switzerland System I: Introduction to Computer Architecture WS 2005-2006 18. January 2006 amos.brocco@unifr.ch (1)

2. Mic-1: Microarchitecture (1) (2)

3. Mic-1: Microarchitecture (2) (3) Data path Control section

4. The data path (4) 32-bit registers (with exception of PC and MDR, which are 8 bit registers) B bus to drive data to the ALU C bus to drive data from the ALU to registers H register as A-input of the ALU ALU with 6 control signals (and 2 outputs, N to test for Negative numbers and Z to test for Zero) From/ To Memory

5. ALU Control Signals (5) 1

6. The data path (6) Registers have control signals to enable/disable reading from them (put value on the B bus) and writing to them (store value from the C bus) It is possible to read only from one register at time: so we can use a 4 -> 16 bit decoder It is possible to write to one or more registers at the same time: so we need 9 control signals for the C bus.

7. Data path synchronization (1) (7) 1.Control signals stabilize 2.A register value is put on the B bus 3.ALU and shifter operate 4.Result propagate on the C bus 5.Result is written in the registers on the raising edge of the next clock pulse

8. Data path synchronization (2) (8) 1.Control signals stabilize 2.Register's value is put on the B bus 3.ALU and shifter operate 4.Result propagate on the C bus 5.Result is written in the registers on the raising edge of the next clock pulse

9. Data path synchronization (3) (9) 1.Control signals stabilize 2.Register's value is put on the B bus 3.ALU and shifter operate 4.Result propagate on the C bus 5.Result is written in the registers on the raising edge of the next clock pulse

10. Data path synchronization (4) (10) 1.Control signals stabilize 2.Register's value is put on the B bus 3.ALU and shifter operate 4.Result propagate on the C bus 5.Result is written in the registers on the raising edge of the next clock pulse

11. Data path synchronization (4) (11) 1.Control signals stabilize 2.Register's value is put on the B bus 3.ALU and shifter operate 4.Result propagate on the C bus 5.Result is written in the registers on the raising edge of the next clock pulse

12. MAR and MDR (1) (12) 32 bit registers connected to the main memory MAR = Memory Address Register MDR = Memory Data Register MAR has only one control signal (input from C) Two memory operations: read and write

13. MAR and MDR (2) (13) Data is word (4*8bit = 32bit in our ISA) addressed! =>MAR addresses are shifted 2bit left ( = * 4)

14. Memory Access (14) A memory read initiated at cycle k delivers data that can be used only in cycle k+2 or later! 1.MAR is loaded 2.Memory access 3.MDR is loaded with data read from memory 4.Data in MDR is available

15. Memory Access (15) A memory read initiated at cycle k delivers data that can be used only in cycle k+2 or later! 1.MAR is loaded 2.Memory access 3.MDR is loaded with data read from memory 4.Data in MDR is available

16. Memory Access (16) A memory read initiated at cycle k delivers data that can be used only in cycle k+2 or later! 1.MAR is loaded 2.Memory access 3.MDR is loaded with data read from memory 4.Data in MDR is available

17. Memory Access (17) A memory read initiated at cycle k delivers data that can be used only in cycle k+2 or later! 1.MAR is loaded 2.Memory access 3.MDR is loaded with data read from memory 4.Data in MDR is available

18. Memory Access (18) A memory read initiated at cycle k delivers data that can be used only in cycle k+2 or later! 1.MAR is loaded 2.Memory access 3.MDR is loaded with data read from memory 4.Data in MDR is available

19. Memory Access (2) (19) Until start of cycle k+2 the MDR register contains old data It is possible to issue consecutive requests, for example at time k and k+1: corresponding results will be available at k+2 and k+3

20. PC and MBR (20) 8 bit registers connected to the main memory used to read (fetch) ISA instructions PC = Program Counter MBR = Memory Buffer Register Access also requires one clock cycle (k -> k+2) MBR has two control signals for the B bus, for signed or unsigned operations One memory operation: fetch

21. H register (21) Is the A-input of the ALU Has only one control signal; output to the ALU is always enabled

22. ISA, IJVM, Microarchitecture (22) ISA = Instruction Set Architecture (defines instructions, memory model, available registers,...) IJVM = An example ISA (it's stack based architecture) The IJVM (Integer Java Virtual Machine) level executes the IJVM Instruction set The IJVM is (in this case) implemented by the Mic-1 Microarchitecture

23. Mic-1 implementation (23) The Mic-1 is a microprogrammed architecture: each IJVM instruction (Macroinstruction) is divided one or more steps. In each step, a microinstruction is executed by the Mic-1. Microinstructions are simpler than ISA macroinstructions.

24. Control section (24) MicroProgram Counter (MPC) Control store holding microinstructions MicroInstruction Register (MIR) containing current microinstruction

25. Microinstructions (25) 36bit wide microinstructions Microinstructions are “executed” in the control section (“a CPU in the CPU”) Microinstructions basically drive control signals for the data path. To avoid the need for a real (micro)Program Counter each microinstruction specifies the address of the following one. Microinstruction addresses are 9-bit wide

26. Microinstruction format (1) (26)

27. Microinstruction format (2) (27) Addr: Address of the next microinstruction

28. Microinstruction format (3) (28) JAM: Determines how to choose next microinstruction

29. Microinstruction format (4) (29) ALU: Control signals to choose ALU operations

30. Microinstruction format (5) (30) C: Enables writing from C bus to the selected registers

31. Microinstruction format (6) (31) Mem: Controls memory read/write/fetch operations

32. Microinstruction format (7) (32) B: Controls which register can write to the B bus

33. Driving control signals (33) 1.MIR is loaded on the falling edge of the clock based on the MPC address, control signals propagate 2.ALU Operation: N and Z values available and saved

34. Driving control signals (34) 1.MIR is loaded on the falling edge of the clock based on the MPC address, control signals propagate 2.ALU Operation: N and Z values available and saved

35. Driving control signals (35) 1.MIR is loaded on the falling edge of the clock based on the MPC address, control signals propagate 2.ALU Operation: N and Z values available and saved

36. Next microinstruction (1) (36) Addr (the address of the next microinstruction coded in the current microinstruction) is copied in the MPC (lower 8 bits, high bit is 0) If J is 000 the next address is in the MPC and the next microinstruction can be read from the control store (Note: microinstruction are not stored in the same order as Figure 4-17) If J is not 000 it is necessary to compute the next microaddress depending on the values of J, N and Z (whose value has been saved in flip-flop because the ALU returns correct result as long as data is passing through it) Addr[8]

37. Next microinstruction (2) (37) If JAMN or JAMZ are set to 1, the 'High bit' function computes the value of the high bit of the MPC as follows: F = (JAMZ and Z) or (JAMN and N) or Addr[8] (To avoid confusion: Addr[8] is in fact the 9 th bit, the highest, of Addr, as bits count start from 0) So the MPC can assume either the value of Addr or the value of Addr with the high bit ORred with 1 Addr[8]

38. Next microinstruction (3) (38) F = (JAMZ and Z) or (JAMN and N) or Addr[8] An example: Let Addr <= 0xFF (or we would get the same value, 0xFF in either case) Let JAMZ = 1 (or JAMN = 1) Let Z=1 (or N=1) in this case MPC is Addr + 0x100 (for example: if Addr=0x92, MPC = 0x92 + 0x100 = 0x192) Note: 0x100 = 256 Addr[8]

39. Microinstructions (4) (39)...but why is all that stuff required to determine the next microinstruction ? Reason: efficiency In case of conditional jumps (if..then..else) we normally need two jump addresses as parameter. To uniform the microinstruction format we want all instruction to have the same length: either we make all microinstruction contain two addresses (-> waste of space) or (better solution) we specify only one address and compute the second one as Addr + Constant Value (in Mic-1 Constant Value = 0x100)

40. Next microinstruction (5) (40) If JMPC = 0, Addr is copied to MPC If JMPC = 1, an the lower 8-bits of Addr are ORred with the MBR value, and the result is put in the MPC Normally when JMPC = 1, Addr is set to either 0x000 or 0x100 JMPC is used to jump to the address specified by the MBR, which, as we will see, contains the opcode of the ISA instruction: in fact, microinstruction for each macroinstruction are stored starting from the position determined by the opcode of the latter. Addr[8]

41. Next microinstruction (6) (41) Example ISA instruction: BIPUSHopcode is 0x10 corresponding microinstructions starts at address 0x10 in the control store For the reasons explained in the previous slides, it is clear that the next microinstruction can be determined only when the MBR, N and Z are ready, i.e. starting from the successive clock pulse) Addr[8]

42. Procedure calls (42) The fact: all programming language support the concept of procedures (methods). Each method has its own local variables that are no more accessible when the procedure has returned. The problem: Where should these variables be kept in memory?

43. Solutions (43) Solution 1: Give each variable its own memory address: but what if the procedures calls itself? Solution 2: Use a data structure called execution stack

44. Execution stack (1) (44) The execution stack is stored in an area of memory It is reserved for storing variables It is possible to push values on the top of the stack or pop values from the top A special register (SP = Stack Pointer) always contains the address of the top of the stack

45. Execution stacks (2) (45) How a stack solves the problem of procedure call ? A special register (LV) stores the base absolute address (position) in the stack from where local variables of the current procedure are stored. Local variables are referred by mean of a relative distance (offset) from the absolute address pointed by LV. The data structure between LV and SP is called local variable frame of the current procedure.

46. Example (1) (46) A procedure 'A', which has local variables a1,a2 and a3 is executing: a1 is at address LV, a2 is at LV+1, a3 is at LV+2 Execution stack Memory

47. Example (2) (47) 'A' calls procedure 'B', which has local variables b1, b2, b3, b4: 'B' local variables are pushed on the stack. LV is updated to point to the address where 'B' local variables start.

48. Example (3) (48) 'B' calls procedure 'C', which has local variables c1 and c2:

49. Example (4) (49) 'A' calls procedure 'D', which has local variables d1, d2, d3, d4 and d5, which are stored at the same location of the “not still available” 'B' and 'C' local variables:

50. Stack based machine (50) IJVM is a stack based machine The stack is also used to store operands during the computation of arithmetic expressions as well as the result; such use is called operand stack Beside access to the main memory, the IJVM only exposes the stack structure to the programmer (no registers are available and in any way directly accessible with the IJVM instruction set)

51. Operand stack (1) (51) Let a1, a2 and a3 be local variables representing integer numbers How to compute a1 = a2 + a3 on a stack based architecture? Note: We suppose to have an instruction that sums the two values on the top of the stack, and pushes the result back on the stack

52. Operand stack (2) (52) First values of a2 and a3 are pushed on the stack:

53. Operand stack (3) (53) Then we execute the instruction for the sum: it will pop the two top-most values on the stack, compute their sum and push the result back on the stack.

54. Operand stack (4) (54) Finally we save back the value at the top of the stack in a1:

55. Memory organization (55) CPP, LV and SP points to 4-byte words, PC points to a byte

56. IJVM ISA (1) (56) 20 Instructions Integer Arithmetic Instruction are composed of an operation code (opcode) and an optional operand (a memory offset or a constant)

57. IJVM ISA (2) (57) Types of instruction: Push a word on stack (LDC_W, ILOAD, BIPUSH) Pop a word from the stack, assign its value to a local variable (POP, ISTORE) Arithmetic (integer) and logic operations (IADD,ISUB,IAND,IOR) Conditional Branching, Jumps (IFEQ, IFLT, IF_ICMPEQ, GOTO) Swapping of values on top of the stack (SWAP) Duplicate value on top of the stack (DUP) Format conversion (prefix instruction WIDE) Method/Procedure call (INVOKEVIRTUAL) Return from a method (IRETURN) NOP INCC Adding a constant to a local variable (INCC)

58. IJVM ISA (3) (58)

59. Example Program (59) Instructions are replaced by Hex opcodes Local variables are stored on the stack and referenced by mean of an offset starting from the LV pointer Operand Stack evolution during execution Instructions are replaced by Hex opcodes JavaJava assembly IJVM program Labels in the assembly code are replaced by effective offsets in the IJVM code (0x0F = 15) F

60. INVOKEVIRTUAL (60) INVOKEVIRTUAL is used to call another method. This instruction allocates the space for the reference of the object (OBJREF) to be called, for the parameters and local variables (Parameter 1, 2, and 3), for the return address (INVOKEVIRTUAL's following instruction) e a pointer to the Caller's LV (pointer to the previous local variable frame) Finally it changes the value of the PC register so that it points to the code of the called method.

61. INVOKEVIRTUAL: Example (1) (61) The program calls the cmp(p1,p2) method, which accepts two parameters, compares them and returns: -1 if p1 < p2 0 if p1 = p2 1 if p1 > p2 The method is called with p1 = -1 and p2 = -10 : we expect that it returns 1..main... LDC_W objref BIPUSH -1 BIPUSH -10 INVOKEVIRTUAL cmp BIPUSH 1 IF_ICMPEQ EQ... EQ:HALT.end-main... SP LV Stack before INVOKEVIRTUAL, current procedure is main

62. INVOKEVIRTUAL: Example (2) (62) objref is a reference to the method stored in the constant pool: it's use is related to the way the Java Virtual Machine operates, but it is not really necessary in our IJVM.main... LDC_W objref BIPUSH -1 BIPUSH -10 INVOKEVIRTUAL cmp BIPUSH 1 IF_ICMPEQ EQ... EQ:HALT.end-main... SP LV objref

63. INVOKEVIRTUAL: Example (3) (63) The first parameter is pushed on the stack: p1 = -1.main... LDC_W objref BIPUSH -1 BIPUSH -10 INVOKEVIRTUAL cmp BIPUSH 1 IF_ICMPEQ EQ... EQ:HALT.end-main... SP LV objref

64. INVOKEVIRTUAL: Example (4) (64) The second parameter is pushed on the stack: p2 = -10.main... LDC_W objref BIPUSH -1 BIPUSH -10 INVOKEVIRTUAL cmp BIPUSH 1 IF_ICMPEQ EQ... EQ:HALT.end-main... SP LV objref -10

65. INVOKEVIRTUAL: Example (5) (65) The method cmp(-1, -10) is invoked.main... LDC_W objref BIPUSH -1 BIPUSH -10 INVOKEVIRTUAL cmp BIPUSH 1 IF_ICMPEQ EQ... EQ:HALT.end-main... SP LV objref -10

66. INVOKEVIRTUAL: Example (6) (66) Before executing the method, some operation must be done: allocate space for and assign values to local variables (temp), save the address of the instruction following the method call (return address) and the LV register (base pointer of the local variable frame of the caller), objref is overwritten with a pointer to address of the return address in the stack. LV is then updated to the current local variable frame start..method cmp(p1,p2).var temp.end-var ILOAD p1 ILOAD p2 ISUB ISTORE temp ILOAD temp IFLT lt ILOAD temp IFEQ eq gt:BIPUSH 1 GOTO done lt:BIPUSH -1 GOTO done eq:BIPUSH 0 done:IRETURN.end-method... SP LV link -10 temp return address LV caller's LV (in this case main's LV) address of the instruction that follows INVOKEVIRTUAL

67. INVOKEVIRTUAL: Example (7) (67) The value of the first parameter is loaded on the stack: p1 = -1.method cmp(p1,p2).var temp.end-var ILOAD p1 ILOAD p2 ISUB ISTORE temp ILOAD temp IFLT lt ILOAD temp IFEQ eq gt:BIPUSH 1 GOTO done lt:BIPUSH -1 GOTO done eq:BIPUSH 0 done:IRETURN.end-method... SP LV link -10 temp return address LV

68. INVOKEVIRTUAL: Example (8) (68) The value of the second parameter is loaded on the stack: p2 = -10.method cmp(p1,p2).var temp.end-var ILOAD p1 ILOAD p2 ISUB ISTORE temp ILOAD temp IFLT lt ILOAD temp IFEQ eq gt:BIPUSH 1 GOTO done lt:BIPUSH -1 GOTO done eq:BIPUSH 0 done:IRETURN.end-method... SP LV link -10 temp return address LV -10

69. INVOKEVIRTUAL: Example (9) (69) Compute the difference (ISUB) between the two values on top of the stack. Push the result back on the stack..method cmp(p1,p2).var temp.end-var ILOAD p1 ILOAD p2 ISUB ISTORE temp ILOAD temp IFLT lt ILOAD temp IFEQ eq gt:BIPUSH 1 GOTO done lt:BIPUSH -1 GOTO done eq:BIPUSH 0 done:IRETURN.end-method... SP LV link -10 temp return address LV 9

70. INVOKEVIRTUAL: Example (10) (70) Save the value on top of the stack in the temp variable. Note: This pulls the top-most value off the stack, so after we need to re-push it..method cmp(p1,p2).var temp.end-var ILOAD p1 ILOAD p2 ISUB ISTORE temp ILOAD temp IFLT lt ILOAD temp IFEQ eq gt:BIPUSH 1 GOTO done lt:BIPUSH -1 GOTO done eq:BIPUSH 0 done:IRETURN.end-method... SP LV link -10 temp: 9 return address 9 LV

71. INVOKEVIRTUAL: Example (11) (71) Load the value of temp on the stack.method cmp(p1,p2).var temp.end-var ILOAD p1 ILOAD p2 ISUB ISTORE temp ILOAD temp IFLT lt ILOAD temp IFEQ eq gt:BIPUSH 1 GOTO done lt:BIPUSH -1 GOTO done eq:BIPUSH 0 done:IRETURN.end-method... SP LV link -10 temp: 9 return address LV 9

72. INVOKEVIRTUAL: Example (12) (72) If the value at the top of the stack is negative (less than 0) jump to 'lt', else continue. The value on top is popped. In this case 9 > 0: we continue....method cmp(p1,p2).var temp.end-var ILOAD p1 ILOAD p2 ISUB ISTORE temp ILOAD temp IFLT lt ILOAD temp IFEQ eq gt:BIPUSH 1 GOTO done lt:BIPUSH -1 GOTO done eq:BIPUSH 0 done:IRETURN.end-method... SP LV link -10 temp: 9 return address 9 LV

73. INVOKEVIRTUAL: Example (13) (73) temp is loaded back on the stack.method cmp(p1,p2).var temp.end-var ILOAD p1 ILOAD p2 ISUB ISTORE temp ILOAD temp IFLT lt ILOAD temp IFEQ eq gt:BIPUSH 1 GOTO done lt:BIPUSH -1 GOTO done eq:BIPUSH 0 done:IRETURN.end-method... SP LV link -10 temp: 9 return address LV 9

74. INVOKEVIRTUAL: Example (14) (74) If the top of the stack is equal to zero jump to 'eq', else continue As we have 9 we continue....method cmp(p1,p2).var temp.end-var ILOAD p1 ILOAD p2 ISUB ISTORE temp ILOAD temp IFLT lt ILOAD temp IFEQ eq gt:BIPUSH 1 GOTO done lt:BIPUSH -1 GOTO done eq:BIPUSH 0 done:IRETURN.end-method... SP LV link -10 temp: 9 return address LV 9

75. INVOKEVIRTUAL: Example (14) (75) The constant value 1 is pushed on the stack (this will be the return value of the cmp method).method cmp(p1,p2).var temp.end-var ILOAD p1 ILOAD p2 ISUB ISTORE temp ILOAD temp IFLT lt ILOAD temp IFEQ eq gt:BIPUSH 1 GOTO done lt:BIPUSH -1 GOTO done eq:BIPUSH 0 done:IRETURN.end-method... SP LV link -10 temp: 9 return address LV 1

76. INVOKEVIRTUAL: Example (15) (76) We jump to 'done'. On top of the stack the return value 1 remains.method cmp(p1,p2).var temp.end-var ILOAD p1 ILOAD p2 ISUB ISTORE temp ILOAD temp IFLT lt ILOAD temp IFEQ eq gt:BIPUSH 1 GOTO done lt:BIPUSH -1 GOTO done eq:BIPUSH 0 done:IRETURN.end-method... SP LV link -10 temp: 9 return address LV 1

77. IRETURN (77) IRETURN is used exit a method and return to the caller This instruction deallocates the stack space reserved for the INVOKEVIRTUAL call, restores the values of the LV and PC registers and assures that the return value is on top of the stack.

78. IRETURN: Example (16) (78) We return to the caller....method cmp(p1,p2).var temp.end-var ILOAD p1 ILOAD p2 ISUB ISTORE temp ILOAD temp IFLT lt ILOAD temp IFEQ eq gt:BIPUSH 1 GOTO done lt:BIPUSH -1 GOTO done eq:BIPUSH 0 done:IRETURN.end-method... SP LV link -10 temp: 9 return address LV 1

79. IRETURN: Example (17) (79) Values of the LV and SP registers are restored, the top of the stack contains the return value of the method, PC is restored to the saved value (return address) so that execution continues from the instruction following the INVOKEVIRTUAL call..method cmp(p1,p2).var temp.end-var ILOAD p1 ILOAD p2 ISUB ISTORE temp ILOAD temp IFLT lt ILOAD temp IFEQ eq gt:BIPUSH 1 GOTO done lt:BIPUSH -1 GOTO done eq:BIPUSH 0 done:IRETURN.end-method... SP LV 1 -10 temp: 9 return address LV 1

80. IRETURN: Example (18) (80) We push the constant 1 on the top of the stack.main... LDC_W objref BIPUSH -1 BIPUSH -10 INVOKEVIRTUAL cmp BIPUSH 1 IF_ICMPEQ EQ... EQ:HALT.end-main... SP LV 1 1

81. IRETURN: Example (19) (81) We compare the two top-most values on the stack. If they are equal (that's the case in this example) jump to 'EQ'..main... LDC_W objref BIPUSH -1 BIPUSH -10 INVOKEVIRTUAL cmp BIPUSH 1 IF_ICMPEQ EQ... EQ:HALT.end-main... SP LV 1 1