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Kazi Fall 2006 EEGN 4941 EEGN-494 HDL Design Principles for VLSI/FPGAs Khurram Kazi Some of the slides were taken from K Gaj’s lecture slides from GMU’s.

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Presentation on theme: "Kazi Fall 2006 EEGN 4941 EEGN-494 HDL Design Principles for VLSI/FPGAs Khurram Kazi Some of the slides were taken from K Gaj’s lecture slides from GMU’s."— Presentation transcript:

1 Kazi Fall 2006 EEGN 4941 EEGN-494 HDL Design Principles for VLSI/FPGAs Khurram Kazi Some of the slides were taken from K Gaj’s lecture slides from GMU’s VHDL course webpage

2 2Kazi Fall 2006 EEGN 494 Anatomy of a Process [label:] process [(sensitivity list)] [VARIABLE name type [range] [:= initial_value;]] begin (sequential code) end process [label]; OPTIONAL

3 3Kazi Fall 2006 EEGN 494 Process: Statement Part Contains Sequential Statements to be Executed Each Time the Process Is Activated Typically a process is activated by any activity on the signals listed in the sensitivity list Condition related to WAIT is fulfilled

4 4Kazi Fall 2006 EEGN 494 A process can be given a unique name using an optional LABEL This is followed by the keyword PROCESS The keyword BEGIN is used to indicate the start of the process All statements within the process are executed SEQUENTIALLY. Hence, order of statements is important. A process must end with the keywords END PROCESS. TESTING: process begin TEST_VECTOR<=“00”; wait for 10 ns; TEST_VECTOR<=“01”; wait for 10 ns; TEST_VECTOR<=“10”; wait for 10 ns; TEST_VECTOR<=“11”; wait for 10 ns; end process; A process is a sequence of instructions referred to as sequential statements. What is a PROCESS? The Keyword PROCESS

5 5Kazi Fall 2006 EEGN 494 Behavioral VHDL (subset) sequential signal assignment (  ) if-then-else statement wait until wait for Major instructions Selected sequential statements

6 6Kazi Fall 2006 EEGN 494 PROCESS with a SENSITIVITY LIST List of signals to which the process is sensitive. Whenever there is an event on any of the signals in the sensitivity list, the process fires. Every time the process fires, it will run in its entirety. WAIT statements are NOT ALLOWED in a processes with SENSITIVITY LIST. label: process (sensitivity list) declaration part begin statement part end process;

7 7Kazi Fall 2006 EEGN 494 Processes in VHDL Processes Describe Sequential Behavior Processes in VHDL Are Very Powerful Statements Allow to define an arbitrary behavior that may be difficult to represent by a real circuit Not every process can be synthesized Use Processes with Caution in the Code to Be Synthesized Use Processes Freely in Testbenches

8 8Kazi Fall 2006 EEGN 494 Component Equivalent of a Process All signals which appear on the left of signal assignment statement (<=) are outputs e.g. y, z All signals which appear on the right of signal assignment statement (<=) or in logic expressions are inputs e.g. w, a, b, c All signals which appear in the sensitivity list are inputs e.g. clk Note that not all inputs need to be included in the sensitivity list priority: PROCESS (clk) BEGIN IF w(3) = '1' THEN y <= "11" ; ELSIF w(2) = '1' THEN y <= "10" ; ELSIF w(1) = c THEN y <= a and b; ELSE z <= "00" ; END IF ; END PROCESS ; w a y z priority b c clk

9 9Kazi Fall 2006 EEGN 494 Registers

10 10Kazi Fall 2006 EEGN 494 ClockD 0 1 1 – 0 1 0 1 Truth table Graphical symbol t 1 t 2 t 3 t 4 Time Clock D Q Timing diagram Q(t+1) Q(t) D latch D Q Clock

11 11Kazi Fall 2006 EEGN 494 Clk D   0 1 0 1 Truth table t 1 t 2 t 3 t 4 Time Clock D Q Timing diagram Q(t+1) Q(t) D flip-flop D Q Clock Graphical symbol 0 – Q(t) 1 –

12 12Kazi Fall 2006 EEGN 494 LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY latch IS PORT ( D, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END latch ; ARCHITECTURE Behavior OF latch IS BEGIN PROCESS ( D, Clock ) BEGIN IF Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior; D latch D Q Clock

13 13Kazi Fall 2006 EEGN 494 LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Clock: INSTD_LOGIC ; Q: OUTSTD_LOGIC) ; END flipflop ; ARCHITECTURE Behavior_1 OF flipflop IS BEGIN PROCESS ( Clock ) BEGIN IF Clock'EVENT AND Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior_1 ; D flip-flop D Q Clock

14 14Kazi Fall 2006 EEGN 494 LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Clock: INSTD_LOGIC ; Q: OUTSTD_LOGIC) ; END flipflop ; ARCHITECTURE Behavior_2 OF flipflop IS BEGIN PROCESS BEGIN WAIT UNTIL Clock'EVENT AND Clock = '1' ; Q <= D ; END PROCESS ; END Behavior_2 ; D flip-flop D Q Clock

15 15Kazi Fall 2006 EEGN 494 LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Resetn, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END flipflop ; ARCHITECTURE Behavior OF flipflop IS BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN Q <= '0' ; ELSIF Clock'EVENT AND Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior ; D flip-flop with asynchronous reset D Q Clock Resetn

16 16Kazi Fall 2006 EEGN 494 LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Resetn, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END flipflop ; ARCHITECTURE Behavior OF flipflop IS BEGIN PROCESS BEGIN WAIT UNTIL Clock'EVENT AND Clock = '1' ; IF Resetn = '0' THEN Q <= '0' ; ELSE Q <= D ; END IF ; END PROCESS ; END Behavior ; D flip-flop with synchronous reset D Q Clock Resetn

17 17Kazi Fall 2006 EEGN 494 8-bit register with asynchronous reset LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY reg8 IS PORT ( D: IN STD_LOGIC_VECTOR(7 DOWNTO 0) ; Resetn, Clock: IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ) ; END reg8 ; ARCHITECTURE Behavior OF reg8 IS BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN Q <= "00000000" ; ELSIF Clock'EVENT AND Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior ;` Resetn Clock reg8 88 DQ

18 18Kazi Fall 2006 EEGN 494 N-bit register with asynchronous reset LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY regn IS GENERIC ( N : INTEGER := 16 ) ; PORT ( D: IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; Resetn, Clock: IN STD_LOGIC ; Q: OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END regn ; ARCHITECTURE Behavior OF regn IS BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN Q '0') ; ELSIF Clock'EVENT AND Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior ; Resetn Clock regn NN DQ

19 19Kazi Fall 2006 EEGN 494 LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY regn IS GENERIC ( N : INTEGER := 8 ) ; PORT (D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; Enable, Clock: IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END regn ; ARCHITECTURE Behavior OF regn IS BEGIN PROCESS (Clock) BEGIN IF (Clock'EVENT AND Clock = '1' ) THEN IF Enable = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior ; N-bit register with enable Q D Enable Clock regn NN

20 20Kazi Fall 2006 EEGN 494 Counters

21 21Kazi Fall 2006 EEGN 494 LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_unsigned.all ; ENTITY upcount IS PORT (Clear, Clock: IN STD_LOGIC ; Q : BUFFER STD_LOGIC_VECTOR(1 DOWNTO 0) ) ; END upcount ; ARCHITECTURE Behavior OF upcount IS BEGIN upcount: PROCESS ( Clock ) BEGIN IF (Clock'EVENT AND Clock = '1') THEN IF Clear = '1' THEN Q <= "00" ; ELSE Q <= Q + “01” ; END IF ; END PROCESS; END Behavior ; 2-bit up-counter with synchronous reset Q Clear Clock upcount 2

22 22Kazi Fall 2006 EEGN 494 LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_unsigned.all ; ENTITY upcount IS PORT ( Clock, Resetn, Enable : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)) ; END upcount ; 4-bit up-counter with asynchronous reset (1) Q Enable Clock upcount 4 Resetn

23 23Kazi Fall 2006 EEGN 494 ARCHITECTURE Behavior OF upcount IS SIGNAL Count : STD_LOGIC_VECTOR (3 DOWNTO 0) ; BEGIN PROCESS ( Clock, Resetn ) BEGIN IF Resetn = '0' THEN Count <= "0000" ; ELSIF (Clock'EVENT AND Clock = '1') THEN IF Enable = '1' THEN Count <= Count + 1 ; END IF ; END PROCESS ; Q <= Count ; END Behavior ; 4-bit up-counter with asynchronous reset (2) Q Enable Clock upcount 4 Resetn

24 24Kazi Fall 2006 EEGN 494 Shift Registers

25 25Kazi Fall 2006 EEGN 494 Shift register DQ Sin Clock DQDQDQ Q(3) Q(2) Q(1)Q(0) Enable

26 26Kazi Fall 2006 EEGN 494 Shift Register With Parallel Load D(3) DQ Clock Enable Sin D(2) DQ D(1) DQ D(0) DQ Q(0)Q(1)Q(2)Q(3) Load

27 27Kazi Fall 2006 EEGN 494 LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY shift4 IS PORT ( D : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; Enable: IN STD_LOGIC ; Load: IN STD_LOGIC ; Sin : IN STD_LOGIC ; Clock : IN STD_LOGIC ; Q : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END shift4 ; 4-bit shift register with parallel load (1) Q Enable Clock shift4 4 D Load Sin 4

28 28Kazi Fall 2006 EEGN 494 ARCHITECTURE Behavior_1 OF shift4 IS BEGIN PROCESS (Clock) BEGIN IF Clock'EVENT AND Clock = '1' THEN IF Load = '1' THEN Q <= D ; ELSIF Enable = ‘1’ THEN Q(0) <= Q(1) ; Q(1) <= Q(2); Q(2) <= Q(3) ; Q(3) <= Sin; END IF ; END PROCESS ; END Behavior_1 ; 4-bit shift register with parallel load (2) Q Enable Clock shift4 4 D Load Sin 4 Another way of writing the code Q(2 downto 0) <= Q(3 downto 1) Q(3) <= Sin;

29 29Kazi Fall 2006 EEGN 494 LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY shiftn IS GENERIC ( N : INTEGER := 8 ) ; PORT (D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; Enable: IN STD_LOGIC ; Load: IN STD_LOGIC ; Sin : IN STD_LOGIC ; Clock : IN STD_LOGIC ; Q : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END shiftn ; N-bit shift register with parallel load (1) Q Enable Clock shiftn N D Load Sin N

30 30Kazi Fall 2006 EEGN 494 ARCHITECTURE Behavior OF shiftn IS BEGIN PROCESS (Clock) BEGIN IF (Clock'EVENT AND Clock = '1' ) THEN IF Load = '1' THEN Q <= D ; ELSIF Enable = ‘1’ THEN Genbits: FOR i IN 0 TO N-2 LOOP Q(i) <= Q(i+1) ; END LOOP ; Q(N-1) <= Sin ; END IF; END PROCESS ; END Behavior ; N-bit shift register with parallel load (2) Q Enable Clock shiftn N D Load Sin N

31 31Kazi Fall 2006 EEGN 494 If Statement

32 32Kazi Fall 2006 EEGN 494 Sequential Statements (1) If Statement else and elsif are optional if boolean expression then statements elsif boolean expression then statements else boolean expression then statements end if;

33 33Kazi Fall 2006 EEGN 494 SELECTOR: process begin WAIT UNTIL Clock'EVENT AND Clock = '1' ; IF Sel = “00” THEN f <= x1; ELSIF Sel = “10” THEN f <= x2; ELSE f <= x3; END IF; end process; If Statement - Example

34 34Kazi Fall 2006 EEGN 494 Structural Design Style

35 35Kazi Fall 2006 EEGN 494 Structural VHDL component instantiation (port map) generate scheme for component instantiations (for-generate) component instantiation with generic (generic map, port map) Major instructions

36 36Kazi Fall 2006 EEGN 494 Structural VHDL component instantiation (port map) generate scheme for component instantiations (for-generate) component instantiation with generic (generic map, port map) Major instructions

37 37Kazi Fall 2006 EEGN 494 Structural description – example (1) library IEEE; use IEEE.std_logic_1164.all; entity FEWGATES is port ( a,b,c,d: in std_logic; y: out std_logic ); end FEWGATES; architecture structural of FEWGATES is component AND2 port ( i1: in std_logic; i2: in std_logic; y: out std_logic ); end component; component OR2 port ( i1: in std_logic; i2: in std_logic; y: out std_logic ); end component; component INVERTER port ( i: in std_logic; o: out std_logic ); end component; signal a_and_b, c_and_d, not_c_and_d: std_logic; begin

38 38Kazi Fall 2006 EEGN 494 Structural description – example (2) u1: and2 port map (i1 => a, i2 => b, y => a_and_b ); u2: and2 port map (i1 => c, i2 => d, y => c_and_d ); u3: inverter port map (i => c_and_d, o => not_c_and_d); u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d, y => y ); end structural;

39 39Kazi Fall 2006 EEGN 494 Assignments 3 & 4

40 40Kazi Fall 2006 EEGN 494 Q1: Test benches: Generator for 4 bit Shift Register ENTITY tb_ShiftReg_Entity IS -- port ( -- ); ARCHITECTURE tb_ShiftReg of tb_ShiftReg_Entity IS Signalclk: STD_LOGIC := ‘0’; Signal sin: STD_LOGIC := ‘0’; Signalenable: STD_LOGIC := ‘0’; Signalsout: STD_LOGIC; Signalcount: INTEGER := 0; COMPONENT ShiftReg PORT ( clk: in STD_LOGIC; sin: in STD_LOGIC; enable: in STD_LOGIC; sout: out STD_LOGIC ); BEGIN UUT: ShiftReg PORT Map ( clk=> clk, sin=> sin, enable=> enable, sout=> sout ); TB : block BEGIN clk <= not clk after 5 ns; enable <= after 35 ns; END block; Counter: PROCESS (enable, clk) BEGIN IF (enable = ‘0’) then count <= 0; ELSIF (clk’event and clk = ‘1’) THEN count <= count + 1; END IF; END PROCESS; Write a process that sends 0s on sout when the count value is 0, 1, 5, 7, 8, 10, 18, 20 For all other values the sout is 1. END tb_ShifteReg; Q1. Observe the output sout and see if it is the same as sin? Q2. If sout is the same as sin, how many cycles later do the values on sin reflect on sout

41 41Kazi Fall 2006 EEGN 494 Q2: Serial to Parallel Converter Use an 8 bit shift register design to make a serial to 8-bit parallel converter i.e. every 8 bits of serial data coming in, 1 byte (8 bits) of data is put out. Inputs will be clk, reset, sin (serial data in) Output will be dout (data out which will be of the form std_logic_vector (7 downto 0)) Input the Following Pattern 1111 0110 0010 1000Design in such a way that of the first byte (of the serial data in) the left most bit should correspond to the bit 7 of dout and the LSB to the bit 0 of dout Hence the dout should have F6 and 28. Modify the testbench to generate F628 pattern.

42 42Kazi Fall 2006 EEGN 494 Q3 16 bit Register Write VHDL code for 16 bit Register (similar to the one on slide 18) Generate at least 10 different 16 input bit patterns and see if they are the same coming out of the Register. Use a testbench generator to generate the input stimulus

43 43Kazi Fall 2006 EEGN 494 Q4 8 bit Up-Counter Write VHDL code for the 8 bit up-counter similar to the one on slide 23. Generate one cycle long pulse whenever the counter reaches the values 10, 20, 36, 48, 63, 119 and 255. (hint: this will require one more output port, that will toggle whenever one of the above count values are decoded) Run the simulations long enough to see that the counter rolls back to 0 after its highest value and continues to count again. Include a testbench that generates the clock, resetn, enable signals.

44 44Kazi Fall 2006 EEGN 494 Written reports should include Description of the design VHDL code with comments Images of the waveforms (you can use ctrl printscreen) If there were any problems encountered, document them also in your reports This assignment is due during the October 12 class. Assignments submitted after that will not be accepted!! Use Oct. 5 th class time to work on the assignment

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