1. ECE 232 L13. Control.1 ©UCB, DAP’ 97 ECE 232 Hardware Organization and Design Lecture 13 Control Design www.ecs.umass.edu/ece/labs/vlsicad/ece232/spr2002/index_232.html

2. ECE 232 L13. Control.2 ©UCB, DAP’ 97 Recap: Summary from last time °5 steps to design a processor 1. Analyze instruction set => datapath requirements 2. Select set of datapath components & establish clock methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic °MIPS makes it easier Instructions same size Source registers always in same place Immediates same size, location Operations always on registers/immediates °Single cycle datapath => CPI=1, CCT => long °Next time: implementing control

3. ECE 232 L13. Control.3 ©UCB, DAP’ 97 Recap: The MIPS Instruction Formats °All MIPS instructions are 32 bits long. The three instruction formats: R-type I-type J-type °The different fields are: op: operation of the instruction rs, rt, rd: the source and destination registers specifier shamt: shift amount funct: selects the variant of the operation in the “op” field address / immediate: address offset or immediate value target address: target address of the jump instruction optarget address 02631 6 bits26 bits oprsrtrdshamtfunct 061116212631 6 bits 5 bits oprsrt immediate 016212631 6 bits16 bits5 bits

4. ECE 232 L13. Control.4 ©UCB, DAP’ 97 Recap: The MIPS Subset °ADD and subtract add rd, rs, rt sub rd, rs, rt °OR Imm: ori rt, rs, imm16 °LOAD and STORE lw rt, rs, imm16 sw rt, rs, imm16 °BRANCH: beq rs, rt, imm16 oprsrtrdshamtfunct 061116212631 6 bits 5 bits oprsrtimmediate 016212631 6 bits16 bits5 bits

5. ECE 232 L13. Control.5 ©UCB, DAP’ 97 Recap: A Single Cycle Datapath °We have everything except control signals (underline) Today’s lecture will show you how to generate the control signals

6. ECE 232 L13. Control.6 ©UCB, DAP’ 97 The Big Picture: Where are We Now? °The Five Classic Components of a Computer °Today’s Topic: Designing the Control for the Single Cycle Datapath Control Datapath Memory Processor Input Output

7. ECE 232 L13. Control.7 ©UCB, DAP’ 97 Outline of Today’s Lecture °Recap and Introduction °Control for Register-Register & Or Immediate instructions °Control signals for Load, Store, Branch, & Jump °Building a local controller: ALU Control °The main controller °Summary

8. ECE 232 L13. Control.8 ©UCB, DAP’ 97 RTL: The Add Instruction °addrd, rs, rt mem[PC]Fetch the instruction from memory R[rd] <- R[rs] + R[rt]The actual operation PC <- PC + 4Calculate the next instruction’s address oprsrtrdshamtfunct 061116212631 6 bits 5 bits

9. ECE 232 L13. Control.9 ©UCB, DAP’ 97 Instruction Fetch Unit at the Beginning of Add °Fetch the instruction from Instruction memory: Instruction <- mem[PC] This is the same for all instructions PC Ext Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_sel imm16 Instruction

10. ECE 232 L13. Control.10 ©UCB, DAP’ 97 The Single Cycle Datapath during Add 32 ALUctr = Add Clk busW RegWr = 1 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst = 1 Extender Mux 32 16 imm16 ALUSrc = 0 ExtOp = x Mux MemtoReg = 0 Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction °R[rd] <- R[rs] + R[rt] 0 1 0 1 01 Imm16RdRsRt oprsrtrdshamtfunct 061116212631 nPC_sel= +4

11. ECE 232 L13. Control.11 ©UCB, DAP’ 97 Instruction Fetch Unit at the End of Add °PC <- PC + 4 This is the same for all instructions except: Branch and Jump Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_sel imm16 Instruction

12. ECE 232 L13. Control.12 ©UCB, DAP’ 97 The Single Cycle Datapath during Or Immediate °R[rt] <- R[rs] or ZeroExt[Imm16] oprsrtimmediate 016212631 32 ALUctr = Clk busW RegWr = 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst = Extender Mux 32 16 imm16 ALUSrc = ExtOp = Mux MemtoReg = Clk Data In WrEn 32 Adr Data Memory 32 MemWr = ALU Instruction Fetch Unit Clk Zero Instruction 0 1 0 1 01 Imm16RdRsRt nPC_sel =

13. ECE 232 L13. Control.13 ©UCB, DAP’ 97 The Single Cycle Datapath during Or Immediate 32 ALUctr = Or Clk busW RegWr = 1 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst = 0 Extender Mux 32 16 imm16 ALUSrc = 1 ExtOp = 0 Mux MemtoReg = 0 Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction °R[rt] <- R[rs] or ZeroExt[Imm16] 0 1 0 1 01 Imm16RdRsRt oprsrtimmediate 016212631 nPC_sel= +4

14. ECE 232 L13. Control.14 ©UCB, DAP’ 97 The Single Cycle Datapath during Load 32 ALUctr = Add Clk busW RegWr = 1 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst = 0 Extender Mux 32 16 imm16 ALUSrc = 1 ExtOp = 1 Mux MemtoReg = 1 Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction 0 1 0 1 01 Imm16RdRsRt °R[rt] <- Data Memory {R[rs] + SignExt[imm16]} oprsrtimmediate 016212631 nPC_sel= +4

15. ECE 232 L13. Control.15 ©UCB, DAP’ 97 The Single Cycle Datapath during Store °Data Memory {R[rs] + SignExt[imm16]} <- R[rt] oprsrtimmediate 016212631 32 ALUctr = Clk busW RegWr = 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst = Extender Mux 32 16 imm16 ALUSrc = ExtOp = Mux MemtoReg = Clk Data In WrEn 32 Adr Data Memory 32 MemWr = ALU Instruction Fetch Unit Clk Zero Instruction 0 1 0 1 01 Imm16RdRsRt nPC_sel =

16. ECE 232 L13. Control.16 ©UCB, DAP’ 97 The Single Cycle Datapath during Store 32 ALUctr = Add Clk busW RegWr = 0 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst = x Extender Mux 32 16 imm16 ALUSrc = 1 ExtOp = 1 Mux MemtoReg = x Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 1 ALU Instruction Fetch Unit Clk Zero Instruction 0 1 0 1 01 Imm16RdRsRt °Data Memory {R[rs] + SignExt[imm16]} <- R[rt] oprsrtimmediate 016212631 nPC_sel= +4

17. ECE 232 L13. Control.17 ©UCB, DAP’ 97 The Single Cycle Datapath during Branch 32 ALUctr = Subtract Clk busW RegWr = 0 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst = x Extender Mux 32 16 imm16 ALUSrc = 0 ExtOp = x Mux MemtoReg = x Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction 0 1 0 1 01 Imm16RdRsRt °if (R[rs] - R[rt] == 0) then Zero <- 1 ; else Zero <- 0 oprsrtimmediate 016212631 nPC_sel= “Br”

18. ECE 232 L13. Control.18 ©UCB, DAP’ 97 Instruction Fetch Unit at the End of Branch °if (Zero == 1) then PC = PC + 4 + SignExt[imm16]*4 ; else PC = PC + 4 oprsrtimmediate 016212631 Adder PC Clk 00 Mux 4 nPC_sel imm16 Adr Inst Memory Instruction

19. ECE 232 L13. Control.19 ©UCB, DAP’ 97 Step 4: Given Datapath: RTL -> Control ALUctr RegDst ALUSrc ExtOp MemtoRegMemWr Equal Instruction Imm16RdRsRt nPC_sel Adr Inst Memory DATA PATH Control Op Fun RegWr

20. ECE 232 L13. Control.20 ©UCB, DAP’ 97 A Summary of Control Signals inst Register Transfer ADDR[rd] <– R[rs] + R[rt];PC <– PC + 4 ALUsrc = RegB, ALUctr = “add”, RegDst = rd, RegWr, nPC_sel = “+4” SUBR[rd] <– R[rs] – R[rt];PC <– PC + 4 ALUsrc = RegB, ALUctr = “sub”, RegDst = rd, RegWr, nPC_sel = “+4” ORiR[rt] <– R[rs] + zero_ext(Imm16); PC <– PC + 4 ALUsrc = Im, Extop = “Z”, ALUctr = “or”, RegDst = rt, RegWr, nPC_sel = “+4” LOADR[rt] <– MEM[ R[rs] + sign_ext(Imm16)];PC <– PC + 4 ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemtoReg, RegDst = rt, RegWr, nPC_sel = “+4” STOREMEM[ R[rs] + sign_ext(Imm16)] <– R[rs];PC <– PC + 4 ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemWr, nPC_sel = “+4” BEQif ( R[rs] == R[rt] ) then PC <– PC + sign_ext(Imm16)] || 00 else PC <– PC + 4 nPC_sel = “Br”, ALUctr = “sub”

21. ECE 232 L13. Control.21 ©UCB, DAP’ 97 A Summary of the Control Signals addsuborilwswbeqjump RegDst ALUSrc MemtoReg RegWrite MemWrite nPCsel Jump ExtOp ALUctr 1 0 0 1 0 0 0 x Add 1 0 0 1 0 0 0 x Subtract 0 1 0 1 0 0 0 0 Or 0 1 1 1 0 0 0 1 Add x 1 x 0 1 0 0 1 x 0 x 0 0 1 0 x Subtract x x x 0 0 0 1 x xxx optarget address oprsrtrdshamtfunct 061116212631 oprsrt immediate R-type I-type J-type add, sub ori, lw, sw, beq jump func op00 0000 00 110110 001110 101100 010000 0010 Appendix A 10 0000See10 0010We Don’t Care :-)

22. ECE 232 L13. Control.22 ©UCB, DAP’ 97 The Concept of Local Decoding Main Control op 6 ALU Control (Local) func N 6 ALUop ALUctr 3 ALU

23. ECE 232 L13. Control.23 ©UCB, DAP’ 97 The Encoding of ALUop °In this exercise, ALUop has to be 2 bits wide to represent: (1) “R-type” instructions “I-type” instructions that require the ALU to perform: -(2) Or, (3) Add, and (4) Subtract °To implement the full MIPS ISA, ALUop has to be 3 bits to represent: (1) “R-type” instructions “I-type” instructions that require the ALU to perform: -(2) Or, (3) Add, (4) Subtract, and (5) And (Example: andi) Main Control op 6 ALU Control (Local) funcN 6 ALUop ALUctr 3 R-typeorilwswbeqjump ALUop (Symbolic)“R-type”OrAdd Subtract xxx ALUop 1 000 100 00 0 01 xxx

24. ECE 232 L13. Control.24 ©UCB, DAP’ 97 The Decoding of the “func” Field R-typeorilwswbeqjump ALUop (Symbolic)“R-type”OrAdd Subtract xxx ALUop 1 000 100 00 0 01 xxx Main Control op 6 ALU Control (Local) func N 6 ALUop ALUctr 3 oprsrtrdshamtfunct 061116212631 R-type funct Instruction Operation 10 0000 10 0010 10 0100 10 0101 10 1010 add subtract and or set-on-less-than ALUctr ALU Operation 000 001 010 110 111 Add Subtract And Or Set-on-less-than Recall ALU Homework (also P. 286 text): ALUctr ALU

25. ECE 232 L13. Control.25 ©UCB, DAP’ 97 The Truth Table for ALUctr R-typeorilwswbeq ALUop (Symbolic) “R-type”OrAdd Subtract ALUop 1 000 100 00 0 01 ALUopfunc bit 000xxxx ALUctrALU Operation Add010 bit 0x1xxxxSubtract110 01xxxxxOr001 1xx0000Add010 1xx0010Subtract110 1xx0100And000 1xx0101Or001 1xx1010Set on <111 funct Instruction Op. 0000 0010 0100 0101 1010 add subtract and or set-on-less-than

26. ECE 232 L13. Control.26 ©UCB, DAP’ 97 The Logic Equation for ALUctr °ALUctr = !ALUop & ALUop + ALUop & !func & func & !func ALUopfunc bit ALUctr 0x1xxxx1 1xx00101 1xx10101 This makes func a don’t care

27. ECE 232 L13. Control.27 ©UCB, DAP’ 97 The Logic Equation for ALUctr ALUopfunc bit 000xxxx1 ALUctr 0x1xxxx1 1xx00001 1xx00101 1xx10101 °ALUctr = !ALUop & !ALUop + ALUop & !func & !func

28. ECE 232 L13. Control.28 ©UCB, DAP’ 97 The Logic Equation for ALUctr ALUopfunc bit ALUctr 01xxxxx1 1xx01011 1xx10101 °ALUctr = !ALUop & ALUop + ALUop & !func & func & !func & func + ALUop & func & !func & func & !func

29. ECE 232 L13. Control.29 ©UCB, DAP’ 97 The ALU Control Block ALU Control (Local) func 3 6 ALUop ALUctr 3 °ALUctr = !ALUop & ALUop + ALUop & !func & func & !func °ALUctr = !ALUop & !ALUop + ALUop & !func & !func °ALUctr = !ALUop & ALUop + ALUop & !func & func & !func & func + ALUop & func & !func & func & !func

30. ECE 232 L13. Control.30 ©UCB, DAP’ 97 Step 5: Logic for each control signal °nPC_sel <= if (OP == BEQ) then EQUAL else 0 °ALUsrc <=if (OP == “Rtype”) then “regB” else “immed” °ALUctr<= if (OP == “Rtype”) then funct elseif (OP == ORi) then “OR” elseif (OP == BEQ) then “sub” else “add” °ExtOp <= _____________ °MemWr<= _____________ °MemtoReg<= _____________ °RegWr:<=_____________ °RegDst:<= _____________

31. ECE 232 L13. Control.31 ©UCB, DAP’ 97 Step 5: Logic for each control signal °nPC_sel <= if (OP == BEQ) then EQUAL else 0 °ALUsrc <=if (OP == “Rtype”) then “regB” else “immed” °ALUctr<= if (OP == “Rtype”) then funct elseif (OP == ORi) then “OR” elseif (OP == BEQ) then “sub” else “add” °ExtOp <= if (OP == ORi) then “zero” else “sign” °MemWr<= (OP == Store) °MemtoReg<= (OP == Load) °RegWr:<= if ((OP == Store) || (OP == BEQ)) then 0 else 1 °RegDst:<= if ((OP == Load) || (OP == ORi)) then 0 else 1

32. ECE 232 L13. Control.32 ©UCB, DAP’ 97 The “Truth Table” for the Main Control Main Control op 6 ALU Control (Local) func 3 6 ALUop ALUctr 3RegDst ALUSrc :

33. ECE 232 L13. Control.33 ©UCB, DAP’ 97 The “Truth Table” for RegWrite R-typeorilwswbeqjump RegWrite111000 op00 000000 110110 001110 101100 010000 0010 °RegWrite = R-type + ori + lw = !op & !op & !op & !op & !op & !op (R-type) + !op & !op & op & op & !op & op (ori) + op & !op & !op & !op & op & op (lw) RegWrite

34. ECE 232 L13. Control.34 ©UCB, DAP’ 97 PLA Implementation of the Main Control RegWrite ALUSrc MemtoReg MemWrite Branch Jump RegDst ExtOp ALUop

35. ECE 232 L13. Control.35 ©UCB, DAP’ 97 A Real MIPS Datapath (CNS T0)

36. ECE 232 L13. Control.36 ©UCB, DAP’ 97 Putting it All Together: A Single Cycle Processor Instr

37. ECE 232 L13. Control.37 ©UCB, DAP’ 97 Worst Case Timing (Load)

38. ECE 232 L13. Control.38 ©UCB, DAP’ 97 Drawback of this Single Cycle Processor °Long cycle time : Cycle time must be long enough for the load instruction: PC’s Clock -to-Q + Instruction Memory Access Time + Register File Access Time + ALU Delay (address calculation) + Data Memory Access Time + Register File Setup Time + Clock Skew °Cycle time for load is much longer than needed for all other instructions

39. ECE 232 L13. Control.39 ©UCB, DAP’ 97 °Single cycle datapath => CPI=1, CCT => long °5 steps to design a processor 1. Analyze instruction set => datapath requirements 2. Select set of datapath components & establish clock methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic °Control is the hard part °MIPS makes control easier Instructions same size Source registers always in same place Immediates same size, location Operations always on registers/immediates Summary Control Datapath Memory Processor Input Output