1. ECE 559 VLSI – Design Project Viterbi Decoder VLSI Design Project Spring 2002 Dan Breen Keith Grimes Damian Nowak David Rust Advisor: Prof. Goeckel

2. ECE 559 VLSI – Design Project Definition of Feasibility Capable of being done or carried out. Reasonable, Likely

3. ECE 559 VLSI – Design Project Digital Communication System Source Encoder Channel Encoder Demodulator Channel Modulator Source Decoder Channel Decoder Source User A/D Conversion Compression “Few Bits” “More Bits” Redundancy to Reduce Probability of Error Viterbi Decoder - with Probability of Error of about 0.00001 Reconstruct Original Signal Guesses the “More Bits” Effective Channel with Probability 0.1 – 0.01 of flipping a bit

4. ECE 559 VLSI – Design Project Parameters Rate = 1/2 Constraint Length (K) = 3

5. ECE 559 VLSI – Design Project Channel Encoder 1-Bit Register Input + + 0 1 0 0 1 1 0 1 0 Output = 00 11 10 Rate = 1/2 K = 3

6. ECE 559 VLSI – Design Project Trellis Diagram – Heart of the Viterbi Decoder Enumerates all possible encoded sequences (basically a FSM transitioning with time)

7. ECE 559 VLSI – Design Project Viterbi Decoder Block Diagram Hamming Distance Compute Metric Path Select Path Memory Compare Select Input Output

8. ECE 559 VLSI – Design Project Hamming Distance Bit-wise XOR comparison of received channel symbol pair and possible channel symbol pairs. I.e. the hamming distance between 01 and 11 would be 1, and the hamming distance between 01 and 10 would be 2.

9. ECE 559 VLSI – Design Project Hamming Distance Module 2 Input 2 2 2 2 Distance with 00 01 10 11

10. ECE 559 VLSI – Design Project Compute Metric Add the previous accumulated error metric to the current calculated hamming distance.

11. ECE 559 VLSI – Design Project Compute Metric Module 2 From Hamming Distance 4 4 2 2 2...... 8 Error Metrics 3333 From Compare Select

12. ECE 559 VLSI – Design Project Compare Select Determines the smallest accumulated error metric entering each state. Reduces magnitude of accumulated error metric to prevent register overflow.

13. ECE 559 VLSI – Design Project Compare Select Module 4 From Compute Metric {0..7} 4 4 4 To Path Memory 3 To Compute Metric...... 333 4 4

14. ECE 559 VLSI – Design Project Path Memory Stores the 4 possible paths through the trellis with their associated accumulated error metrics. Retains at least 5 * (K-1) previous trellis stages.

15. ECE 559 VLSI – Design Project Path Memory Module 4 From Compare Select {0..3} 4 4 4...... To Path Select {0..3}......

16. ECE 559 VLSI – Design Project Path Select Selects path with the lowest accumulated error metric and performs traceback and decoding.

17. ECE 559 VLSI – Design Project Path Select Module 4 From Path Memory {0..3} 4 Decoded Output...... 1

18. ECE 559 VLSI – Design Project

19. ECE 559 VLSI – Design Project Conclusion Yes…It is Feasible. Next…complete modules and perform testing and verification of Viterbi decoder.

20. ECE 559 VLSI – Design Project References 1.Communication Systems Engineering, 1 st edition (1994). John G. Proakis and Masoud Salehi. Prentice Hall. 2.“Lecture #14: Convolutional Codes” (Fall 1992). Kim Winick. 3.“A Tutorial on Convolutional Coding with Viterbi Decoder” (Nov 2001). Chip Fleming. 4.Advisor Lecture Notes (Feb 2002). Dennis Goeckel. 5.http://www.m-w.com/cgi-bin/dictionary Project Web Page http://home.attbi.com/~dlrust/Viterbi.html