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EEG Machine By The All-American Boys Featuring Slo- Mo Motaz Alturayef Shawn Arni Adam Bierman Jon Ohman
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High Level Block Diagram
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Processor Schematic
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FPGA Daughter Board JTAG PowerA2D
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FPGA Pins Bank 1Bank 2 Bank 3Bank 4
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RS232
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Push Buttons, Switches & LEDs
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Sample Code using Nios II IP Core – Ex. SPI Void A2D_T (unsigned char ch){ while (true) { if(IOWR_ALTERA_AVALON_SPI_STATUS(base, data) &0x040) { IOWR_ALTERA_AVALON_SPI_TXDATA(base, data) } }}
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Testing Memory Storage – Inputs stored then flash LEDs – FFT analysis to Nios II console RS232 – TX & RX LEDs, PC use User Output – Flash On-board LED with Goggles
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Electrode Input Schematic
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Part Selection Op-Amp Choice: – Burr-Brown OPA27 Ultra low-noise amplifiers Differential Amp Choice: – Burr-Brown INA105 Ultra low-noise amplifiers Resistor Choice – Using 1% tolerance, should be well matched enough Have.1% tolerance options picked out if necessary
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Filter Selection Using Sallen-Key low-pass filter – Corner at 100Hz – 40dB/dec decrease – Simple, easily expanded if necessary – Should filter out high frequency noise components to neural signal Filter not designed to filter out all environmental noise
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Power Input circuit powered separately from rest of device – Safety: Don’t want any risk with a person attached to one end – Noise: High frequency components of processor could infect power lines – Introduce artifacts into signal
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Power cont’d Input board powered by 9V battery – Voltage inverted to provide negative voltage for amplifier operation
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Testing Testing will be done on PCB – Voltage injections at specific input sites – Measure response for each stage functionality Expect to see: – Amplification of 100x – Single summed output signal – Frequencies over 100Hz are not passed – Noise levels are minimized
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Design Change to Contact No headband – Movement and friction will introduce too many artifacts Conductive paste will be necessary – Metal/Skin interface is not good enough to conduct strong signals Epoxy cast contact with double-sided adhesive to form “well” for paste
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Risks to Design/Implementation Cannot get usable signal from head contacts – Purchase commercial contacts Low-Pass Filter not sufficient at eliminating excess signal information – Cascade to increase effectiveness – Use Different Design Too much noise on the signal line – Increase contact surface area Increase signal strength – Isolate board through effective shielding
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Output Component Changes Previous output components: – Audio CODEC – Monitor to display visual stimulus Current output components: – Separate ADC and DAC Input signal is not being output as auditory stimulus – LED mounted glasses or goggles for visual stimulus Eliminates the need for VGA circuit
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ADC Architectures
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Analog to Digital Converter 16-Bit Resolution Low Noise Performance Low Power Consumption Sigma-Delta Architecture Serial SPI Communication Constant Output
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Digital to Analog Converter 16 Bit Resolution Serial I 2 C Interface 4 Channel Output Low Power Operation Output Directly to Headphones
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Visual Stimulus Example of Glasses
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Testing Mount ADC to through-hole adapter Input sinusoidal signal View output on multi-meter Mount DAC to through-hole adapter Input digital values from FPGA flash View output on oscilloscope
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LabView code for PSD
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The test used a.wav file The left graph is the time domain The right graph is the power spectrum. Test Results
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Serial interface
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Buck conveter Buck converter used to supply enough current to the board. (LM2676-3.3) VCCIO will power VCCIO1, VCCIO2, VCCIO3 and VCCIO4. VCC33 will power the ADC and the DAC chips. MAX232 need 3.3v so will use VCC33 Memory
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Power for Daughter Board
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Voltage Regulator and Clock Voltage regulator with 1.2v output (LM1117-1.2-0.8A) VCC12 is the input for VCCD_PLL1, VCCD_PLL2, VCCA_PLL1 and VCCA_PLLA. The clock is 50MHz
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Schedule
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Questions?
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