1. CIS429.S00: Lec7- 1 Instruction Set Architectures (cont) History Addressing Modes --> Types of Instructions --> Encoding Instructions --> DLX Instruction Set

2. CIS429.S00: Lec7- 2 Types of instructions (by operation ) arithmetic/logical data movement control floating point decimal string graphics

3. CIS429.S00: Lec7- 3 Top ten 80x86 instructions

4. CIS429.S00: Lec7- 4 Control flow instructions conditional branchesBEQZ HOME unconditional branches or jumps JMP ROPE procedure call procedure return Target of the branch can be specified as explicit directJMP ROPE explicit indirectJMP (R1) displacementJMP 100(R2) PC relative JMP 100(PC)

5. CIS429.S00: Lec7- 5 Use of branches in benchmarks

6. CIS429.S00: Lec7- 6 Displacements used in branches x axis gives number of bits 5-6 bits captures most of the displacements

7. CIS429.S00: Lec7- 7 Instruction encoding issues total size(s) of instructions (halfword, word, doubleword) number of fields, number of operands number of bits for each field Dependent on: number of registers types of instructions (operations) addressing modes etc.

8. CIS429.S00: Lec7- 8 Basic varieties of instruction encoding: variable, fixed, hybrid

9. CIS429.S00: Lec7- 9 DLX Architecture Registers 32 32-bit general purpose registers R0, R1, R2 ….. R31 32 32-bit floating points registers single precision F0, F1, … F31 double precision F0, F2, … F30 (even-odd pairs)

10. CIS429.S00: Lec7- 10 DLX Architecture (cont) Data types Integer data types byte (8 bits), halfword (16 bits), word (32 bits) Floating point data types (IEEE 754) single precision (32 bits) double precision (64 bits)

11. CIS429.S00: Lec7- 11 DLX Architecture (cont) Addressing modes (looks like four, only two) Immediate - 16 bits ADD R1, R2,#3 Displacement - 16 bits LW R1,30(R2) Registered deferred/indirect - use 0 displacement LW R1,0(R2) Absolute - use R0 as the base, R0 = 0 LW R1,508(R0)

12. CIS429.S00: Lec7- 12 DLX Instruction Format

13. CIS429.S00: Lec7- 13 Deciphering DLX notation LW R1,30(R2) Regs[R1] <-- 32 Mem[30 + Regs[R2]] LH R1,40(R3) Regs[R1] <-- 32 (Mem[40 + Regs[R3] 0 ) ## Mem[40 + Regs[R3]] ## Mem[41 + Regs[R3]] Load halfword Duplicate the sign bit, concatenate with the byte at Mem[40 + Regs[R3]] and concatenate with the byte at Mem[41 + Regs[R3]]. This makes a total of 32 bits.

14. CIS429.S00: Lec7- 14 Deciphering DLX notation JAL NAME R31 <-- PC + 4 save return addr PC <-- NAME ((PC + 4) - 2 <= NAME < ((PC + 4) + 2 ) Check bounds on value of NAME since this uses PC relative addressing Used for subroutine calls: