1. 11/3/2004EE 42 fall 2004 lecture 271 Lecture #27 MOS LAST TIME: NMOS Electrical Model – Describing the I-V Characteristics – Evaluating the effective resistance R – Switching behavior TODAY: NMOS physical structure: W and L and d ox, PMOS –Transistor Geometry and capacitance –Scaling of properties with size: ID and C

2. 11/3/2004EE 42 fall 2004 lecture 272 The circuit symbol NMOS as a Switch - Summary G S D IDID N Ch I DS IDID V DS V DD The value of R DN is chosen to predict the correct timing delay. Then we can essentially replace the transistor with the simple switch model (valid of course only for predicting timing delays). Electrical Model D S G R DN If V GS = 0. I D for V GS = maximum (V DD ) We have an equation for I D in the saturation region.

3. 11/3/2004EE 42 fall 2004 lecture 273 For simple digital circuit calculations the MOS transistor will be essentially off (V GS < V T ) or fully turned on (V GS = V DD ), the power supply voltage). In the saturation region we describe the variation of I D with V DS with the empirical equation : MOS “Theory” V GS S G V DS iDiD +  +-+- D I D = I DS X (1+ V DS ) I DS is the intercept with I D axis  is intercept with V DS axis) I DS is slope I DS IDID V DS V GS = V DD off on Then we can estimate the effective resistance in terms of and I DS

4. 11/3/2004EE 42 fall 2004 lecture 274 The effective resistance with V GS = V DD The MOS transistor discharges C. (V DD to V DD /2) As V OUT goes from V DD to V DD /2, the average voltage V DS is (3/4) V DD. Since I D = I DS ( 1+ XV DS ) The average current is I DS ( 1+ X(3/4)V DD ). Using a resistance of this value we get discharge time estimate which is less than 4% different from the correct answer obtained by direct integration - V IN =3V V OUT + - D G S C + -+ - I DS IDID V DS V GS = V DD V GS = 0 V DD V DD /2 Thus the average effective resistance is the ratio: (3/4) V DD / I DS ( 1+ X(3/4)V DD ) = R DN slope = 1/ R DN

5. 11/3/2004EE 42 fall 2004 lecture 275 For simple digital circuit calculations the MOS transistor will be essentially off (V GS < V T ) or fully turned on (V GS = V DD ), the power supply voltage). MOS I-V Characteristics in more detail V GS S G V DS iDiD +  +-+- D I D = I DS X (1+ V DS ) I DS IDID V DS V GS = V DD off on But if V GS = V DD the value of I DS depends on V GS, so we need some more theory. In particular we want to: 1)Describe dependence of I DS on V GS and geometry 2)Describe the “break point” in V DS above which I D saturates.

6. 11/3/2004EE 42 fall 2004 lecture 276 A little more MOS “Theory” We have two regions: the resistive region at smaller V DS and the saturation region at higher V DS. IDID V DS V GS In the resistive region we start out like a simple resistor between source and drain (whose value depends on gate voltage) and gradually the curve “bends over” as we approach saturation In the saturation we have a small gradual increase of I with V DS V GS S G V DS iDiD +  +-+- D We call the boundary between the regions V DSat. V DSat Now we wish to describe the dependence of the current on V GS

7. 11/3/2004EE 42 fall 2004 lecture 277 n P oxide insulator n drain - + source gate Below threshold V GS < V t Below threshold, there are no electrons under the gate oxide, and the holes in the substrate are blocked from carrying current by reverse biased diode junctions

8. 11/3/2004EE 42 fall 2004 lecture 278 n P oxide insulator n drain - + source gate NMOS in the linear (Triode) region V GS > V t If the gate voltage is above threshold, but the source to drain voltage is small, the charge under the gate is uniform, and carries current much like a resistor The electrons move under the influence of the Electric field at a velocity: ν=μE where E=volts/distance And they must travel a distance L to cross the gate Since the total charge is Q=CV gs, we will have a current I d =μC gate V ds (V gs -V th )/L 2 = μ(ε ox /d ox )V ds (V gs -V th )W/L

9. 11/3/2004EE 42 fall 2004 lecture 279 n P oxide insulator n drain - + source gate NMOS with increasing V ds V GS > V t As the voltage from the source to the drain is increased, the current increases, but not by as much because the charge is attracted out from under the oxide, beginning to pinch off the channel

10. 11/3/2004EE 42 fall 2004 lecture 2710 Saturation As the Source-Drain voltage is increased, there will be a significant change in the charge at different distances along the gate When the voltage across the device at the drain end goes below threshold, the current is pinched off. If there is no current out the drain end, however, the current due to the carriers which are available from the source cause the voltage to be closer to that of the source. These two effects cause a small region to form near the drain which limits the current. This is called saturation

11. 11/3/2004EE 42 fall 2004 lecture 2711 n P oxide insulator n drain - + source gate NMOS in saturation V GS > V t When the voltage from the source to the drain gets high enough, the channel gets “pinched” In the pinch region, the carriers move very fast, but the current is determined by the triangular region, which does not change much as the drain voltage is changed, so the current saturates

12. 11/3/2004EE 42 fall 2004 lecture 2712 Submicron MOS In the last few years, transistors have become so small that some of these approximations are breaking down: As the transistors get short, the difference between the triode region and saturation has become blurred, with no clear saturation Because gate oxides are so thin, some current goes through the gate in a process called tunneling Sub-Threshold currents are increasing, causing the transistors to conduct a small amount even when they are supposed to be off.

13. 11/3/2004EE 42 fall 2004 lecture 2713 MOS “Theory”, con’t In the saturation region (V DS >V DSat ) all the curves are described by I D = I DS X (1+ V DS ) but I DS is a function of V GS. In modern devices the saturation current is proportional to (V GS -V T ). The simple field effect gives us the idea for this proportionality: As we increase V GS there is some “threshold”, V T. above which electrons accumulate on the surface. The current is of course proportional to the number of these electrons, so it is proportional to (V GS -V T ). In figure below V T = 1V. Note that the current is proportional to (V GS -V T ), for example the current at V GS =3V is double that at V GS =2V. The intercepts with the current axis ( I DS ) depends not only on the gate voltage, but also on device geometry. We will next discuss how I DS depends on device geometry. IDID V DS V GS V DSat 1/ V GS = 4 V GS = 3 V GS = 2

14. 11/3/2004EE 42 fall 2004 lecture 2714 NMOS TRANSISTOR STRUCTURE NMOS = N-channel Metal Oxide Silicon Transistor n P-type Silicon oxide insulator gate n “Metal” gate (Al or Si) W L Contact to Source Contact to Drain

15. 11/3/2004EE 42 fall 2004 lecture 2715 gate length The gate length, L, is the distance the electrons have to travel. It is generally set at the minimum value (eg.18 micron) for nearly all logic transistors As the gate length gets shorter, the gate capacitance gets smaller As the gate length gets shorter, the current drive of the transistor also gets larger. However, leakage current also increases

16. 11/3/2004EE 42 fall 2004 lecture 2716 Gate width The gate width, W, is determined by the circuit designer. One uses a wider gate to get more current (and thus charge a capacitor faster). For example doubling W is the same as putting two equal-sized transistors in parallel, and thus doubles the current at any given voltage.

17. 11/3/2004EE 42 fall 2004 lecture 2717 The capacitance is proportional to W and L (for logic, mostly L is fixed, so in effect C is proportional to the gate width W that the designer chooses. It is inversely proportional to d OX. n P-type Silicon oxide insulator gate n “Metal” gate (Al or Si) W L Contact to Source Contact to Drain The gate is insulated from the rest of the transistors, but it has a substantial capacitance to the source as it builds up charge in the channel d OX = oxide thickness NMOS TRANSISTOR CAPACITANCE

18. 11/3/2004EE 42 fall 2004 lecture 2718 MOS TRANSISTOR – TOP VIEW Thin oxide Gate (over oxide) Drain contact Source contact What are device dimensions? Gate Length = L and is fixed for any technology. (Such as the.09-0.18  m technology in manufacturing today). Gate Width = W and is selected by the circuit designer for the current required. L W The device current is proportional to W as well as (V GS -V T ), so we express I DS as a constant times ( I DS ' ) times W times (V GS -V T ). ( Thus the units of the constant I DS ' are  A/V-  m.) We multiply I DS ' by the gate width W and by (V GS - V T ). to get the value of I DS in  A. I D = I DS X (1+ V DS ) and I DS = W X I DS ' (V GS -V T ). Example: a “1/4  m device” with I DS ' = 75  A/V-  m, W = 5  m, = 0.02 V - 1, V T = 0.5V and in a circuit with V DD = 2.5V. If the device were 5  m wide and the gate were at V DD then I DS = 5 X 75 (2.5 -0.5) = 750  A.

19. 11/3/2004EE 42 fall 2004 lecture 2719 MOS TRANSISTOR – TOP VIEW Gate Capacitance: The dimensions of the capacitor are area = W X L and thickness = d OX. A typical value, say for “1/4  m” technology, is 5nm. L Gate (over oxide) Drain contact Source contact W The capacitance formula from physics is C= ε A/d = W X L X  OX / d OX. The dielectric constant for oxide,  OX, is 3.9  O = 3.45X10 -13 f/cm. If d OX = 5nm then  OX / d OX =7fF/  m 2 of capacitor so C=7W X L (fF) with W and L in  m. Example: The same “1/4  m device” device with, W = 5  m. The gate capacitance is 5 X 0.25 X 7 fF = 8.6 fF.

20. 11/3/2004EE 42 fall 2004 lecture 2720 V IN jumps from 0V to 3V Controlled Switch Model of Inverter (Lect. 18) If there is a capacitance at the output node (there always is) then V OUT responds to a change in V IN with our usual exponential form. V OUT t Output when V IN jumps from 3V to 0V RNRN + - - V DD = 3V V SS = 0V V IN =3V V OUT + - - V DD = 3V V SS = 0V V IN =0V RPRP V OUT 3 0 This is what we use the NMOS for

21. 11/3/2004EE 42 fall 2004 lecture 2721 Purpose of the NMOS Switch The MOS transistor discharges C (some load). The NMOS switch is great for discharging a node to ground. When V IN goes high (V DD ) then V OUT goes from V DD to ground. When it reaches V DD /2 we call that time the stage delay. But we also need a switch to charge a node, i.e. bring it from ground up toward V DD. That’s where we need another type of transistor, the PMOS. It makes the ideal switch to charge the node. - V IN =3V V OUT + - D G S C + -+ - I DS IDID V DS V GS = V DD V DD V DD /2

22. 11/3/2004EE 42 fall 2004 lecture 2722 NMOS circuit symbol CIRCUIT SYMBOLS G S D A small circle is drawn at the gate to remind us that the polarities are reversed for PMOS. PMOS circuit symbol G S D

23. 11/3/2004EE 42 fall 2004 lecture 2723 n P oxide insulator n drain - + source gate NMOS =device which carrier current using electrons but on the surface of a p-type substrate (p-type substrate means that no electrons are available) n P oxide insulator n drain source N-MOS In this device the gate controls electron flow from source to drain. (in the absence of gate voltage, current is blocked) gate V GS > V t If we increase gate voltage to a value greater than V t then a conducting channel forms between source and drain. (“Closed switch”)

24. 11/3/2004EE 42 fall 2004 lecture 2724 CMOS = Complementary MOS (PMOS is a second Flavor) n P oxide insulator n drain source N-MOS In this device the gate controls electron flow from source to drain. The NEW FLAVOR! P-MOS It is made in p-type silicon. It is made in n-type silicon. (In n- type silicon no positive charges (“holes”) are normally around.) In this device the gate controls hole flow from source to drain. gate source drain n-type Si P-MOS gate pp

25. 11/3/2004EE 42 fall 2004 lecture 2725 PMOS The body is n-type silicon. In this device the gate controls hole flow from source to drain. source drain n-type Si p gate + - p What if we apply a big negative voltage on the gate? If |V GS |>|V t | (both negative) then we induce a + charge on the surface (holes) source drain n-type Si P-MOS gate pp |V GS |>|V t |

26. 11/3/2004EE 42 fall 2004 lecture 2726 NMOS and PMOS Compared NMOS “Body” –p-type Source – n-type Drain – n-type V GS – positive V T – positive V DS – positive I D – positive (into drain) PMOS “Body” –n-type Source – p-type Drain – p-type V GS – negative V T – negative V DS – negative I D – negative (into drain) G n n IDID D S p B G pp IDID D S n B IDID 4 3 2 1 V DS V GS =3V 1 mA V GS =0 (for I DS = 1mA) 4 3 2 1  V DS V GS =  3V 1 mA V GS =0 IDID (for I DS = -1mA)

27. 11/3/2004EE 42 fall 2004 lecture 2727 PMOS Transistor Switch Model Operation compared to NMOS: It is complementary. For PMOS for the normal circuit connection is to connect S to VDD (The function of the device is a “pull up”) V G = V DD Switch is open : Drain (D) is disconnected from Source (S) when V G = V DD V G =0 Switch is closed: Drain (D) is connected to Source (S) when V G =0 G S D V DD Switch OPEN V DD G S D V=0 Switch CLOSED S D G

28. 11/3/2004EE 42 fall 2004 lecture 2728 PMOS Model Refinement PMOS transistor has an equivalent resistance R DP when closed The circuit symbol G D S P Ch S D G R DP The Switch model CGSCGS There is also a gate capacitance C GS, just as in NMOS

29. 11/3/2004EE 42 fall 2004 lecture 2729 CMOS Challenge: build both NMOS and PMOS on a single silicon chip NMOS needs a p-type substrate PMOS needs an n-type substrate Requires extra process steps oxide P-Si n-well ppnn G D G D S S