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Characterization of a CMOS cell library for low-voltage operation
Department of Electrical and Computer Engineering Jia Yao
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Low-power and Low-voltage
Pavg = Pdyn + Pstatic Pdyn = Ptran + Pshort-circuit Ptran = α * C * Vdd 2 * f Pshort-circuit = Isc * Vdd CMOS: dynamic power Reduction of the power supply voltage is the most efficient way to reduce the power consumption.
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Concentration Study TSMC 0.18um standard cell library
Design basic CMOS cells in Hspice and run simulation Apply supply voltage from high to low to observe the influence of lowering Vdd Collect data and arrive to conclusion
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Basic Parameters The environment temperature : 25 ℃
Input pulse T=24ns, and the width of input pulse is 12ns, so the frequency is 41.6MHz. Input slew : 0.03ns Channel length L=0.2um Width Wn=2um, Wp=2.4um Nmos:VTH0 = Pmos: VTH0 =
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Without and with outloading
Calculation Gate Delay= (tphl+ tplh)/2 For two or more inputs gate, calculate delay separately. 1. Gate Delay Vdd/2 Vdd tphl tplh in Vdd Vdd/2 Vdd/2 A Y tphl tplh B out Vdd Without and with outloading Vdd/2 Vdd/2 A Y Y’ B
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Calculation 2. Power Calculation ※ Average power and Peak power
※ For two or more inputs, calculate power separately, keep only one signal changing at one time. ※ Without and with outloading
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Inverter 2.5v 2.0v 1.8v 1.5v 1.2v 1.0v 0.8v 0.5v A→Y↓ (ns) 0.0092 0.019 0.0113 0.021 0.0126 0.023 0.0151 0.026 0.0189 0.033 0.0240 0.042 0.0377 0.068 0.7660 1.266 A→Y↑ 0.015 0.030 0.018 0.036 0.039 0.048 0.031 0.065 0.043 0.092 0.081 0.176 2.420 5.036 Delay 0.012 0.025 0.029 0.016 0.037 0.049 0.034 0.067 0.059 0.122 1.593 3.151 Avg Power (uW/Mhz) 0.0558 0.1975 0.0357 0.1224 0.0293 0.0981 0.0210 0.0674 0.0149 0.0429 0.0109 0.0297 0.0074 0.0188 0.0029 0.0064 Peak Power 32.29 48.76 25.32 39.73 17.76 26.83 13.48 15.09 9.71 8.40 4.62 3.23 0.14 0.09 Power-Delay Product (e-17) 0.0682 0.489 0.0519 0.350 0.0465 0.305 0.0400 0.248 0.0371 0.209 0.0367 0.200 0.0439 0.299 0.4714 2.020
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Power-Delay Product
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Comparison : with and without outloading
Delay Avg Power Peak Power Power-Delay Product
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Nand2
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2.5v 2.0v 1.8v 1.5v 1.2v 1.0v 0.8v 0.5v A→Y↓ (ns) 0.016 0.029 0.018 0.033 0.020 0.035 0.023 0.042 0.031 0.055 0.040 0.077 0.083 0.143 2.4 2.987 A→Y↑ 0.034 0.021 0.044 0.028 0.054 0.038 0.073 0.104 0.107 0.196 3.280 5.392 Delay 0.017 0.036 0.026 0.048 0.064 0.090 0.095 0.170 2.842 4.190 Avg Power (uW/Mhz) 0.0789 0.2290 0.0504 0.1404 0.0412 0.1120 0.0293 0.0764 0.0195 0.0483 0.0132 0.0333 0.0094 0.0209 0.0036 0.0066 Peak Power 48.25 63.32 30.81 38.17 24.71 29.62 17.66 18.27 10.18 9.08 5.51 4.50 1.90 1.46 0.09 0.11 Power-Delay Product (e-16) 0.0134 0.0719 0.0099 0.0511 0.0088 0.0445 0.0075 0.0364 0.0068 0.0310 0.0063 0.0301 0.0089 0.0354 0.1029 0.2760
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2.5v 2.0v 1.8v 1.5v 1.2v 1.0v 0.8v 0.5v B→Y↓ (ns) 0.019 0.032 0.022 0.036 0.024 0.039 0.029 0.046 0.037 0.061 0.053 0.083 0.096 0.015 2.383 3.762 B→Y↑ 0.025 0.041 0.030 0.049 0.033 0.054 0.066 0.058 0.089 0.082 0.125 0.152 0.230 3.989 6.091 Delay 0.026 0.043 0.047 0.035 0.056 0.075 0.068 0.104 0.124 0.122 3.168 4.927 Avg Power (uW/Mhz) 0.1190 0.2903 0.7660 0.1779 0.0625 0.1420 0.0442 0.0964 0.0284 0.0604 0.0202 0.0413 0.0126 0.0255 0.0035 0.0063 Peak Power 57.80 64.08 36.44 38.32 28.99 29.34 17.92 18.02 9.40 8.54 6.04 2.93 0.05 Power-Delay Product (e-16) 0.0257 0.105 0.0198 0.0756 0.0178 0.0664 0.0155 0.0543 0.0134 0.0454 0.0136 0.0429 0.0156 0.0312 0.1115 0.3108
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Comparison : with and without outloading
Delay Avg Power Peak Power Power-Delay Product
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NOR2
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2.5v 2.0v 1.8v 1.5v 1.2v 1.0v 0.8v 0.5v A→Y↓ (ns) 0.013 0.022 0.015 0.024 0.016 0.026 0.018 0.029 0.023 0.036 0.047 0.075 1.005 1.660 A→Y↑ 0.027 0.06 0.032 0.07 0.037 0.08 0.100 0.067 0.14 0.011 0.22 0.242 0.45 7.938 11.96 Delay 0.020 0.041 0.049 0.053 0.033 0.065 0.045 0.090 0.131 0.145 0.264 4.471 6.812 Avg Power (uW/Mhz) 0.0775 0.2298 0.0500 0.1399 0.1108 0.0294 0.0745 0.0189 0.0465 0.0139 0.0319 0.0091 0.0201 0.0034 0.0054 Peak Power 64.91 83.87 42.72 54.07 33.62 43.32 24.49 28.59 16.20 15.69 10.36 8.62 4.50 3.32 0.12 1.13 Power-Delay Product (e-16) 0.0154 0.0940 0.0119 0.0679 0.0108 0.0592 0.0096 0.0487 0.0085 0.0420 0.0028 0.0133 0.0530 0.1532 0.3658
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2.5v 2.0v 1.8v 1.5v 1.2v 1.0v 0.8v 0.5v B→Y↓ (ns) 0.015 0.024 0.017 0.027 0.018 0.028 0.021 0.032 0.026 0.040 0.034 0.051 0.055 0.082 1.104 1.762 B→Y↑ 0.07 0.08 0.045 0.09 0.058 0.11 0.083 0.15 0.125 0.22 0.256 0.44 7.141 11.75 Delay 0.029 0.053 0.039 0.071 0.096 0.079 0.136 0.155 0.262 4.122 0.6756 Avg Power (uW/Mhz) 0.100 0.2505 0.0647 0.1526 0.0524 0.1209 0.0368 0.0810 0.0235 0.0500 0.0162 0.0399 0.0101 0.0209 0.0033 0.0054 Peak Power 70.48 85.80 45.92 54.08 37.06 42.85 26.05 27.65 15.04 14.75 8.52 7.93 3.30 2.96 0.05 Power-Delay Product (e-16) 0.0240 0.1124 0.0186 0.0812 0.0166 0.0706 0.0145 0.0573 0.0129 0.0478 0.0460 0.0156 0.0548 0.1349 0.3630
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Comparison : with and without outloading
Delay Avg Power Peak Power Power-Delay Product
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Review Around 1 V With and without outloading Separate calculation
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Reference Class notes and slides from ELEC6270 by Dr. Agrawal
2. TSMC 0.18 um standard cell library data book 3. Hspice user guide Boarh,M.; Owens, R.M.and Irwin, M.J, “Transistor sizing For low power CMOS circuits’’ IEEE Trans. On Computer- Aided Design of Integrated Circuits and System, vol.15, pp , 1996
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