1. ARM – Asynchronous RISC Microprocessor הטכניון - מכון טכנולוגי לישראל המעבדה למערכות ספרתיות מהירות הפקולטה להנדסת חשמל Submitted by: Tziki Oz-Sinay, Ori Lempel Supervised by: Roni Mittleman

2. General Overview The benefits of asynchronous VLSI circuit design include: Elimination of clock skew problems Average case performance Adaptivity to processing and environmental variations Lower system power requirement Reduced noise

3. Project Description Altera APEX 20K SDRAM 32MB SDRAM 32MB RS232 PCI Interface Data Cache Inst Cache Watch Window (debug) Program Code (assembler)

4. ARM Architecture Register Set: The ARM provides 8 16-bit general-purpose data registers Memory Management: –Separate instruction memory and data memory, each having an address space of up to 64Kbytes. –Both memory spaces are layed out in Little-Endian format.

5. Instruction Set OpCode 4 RxRyImm 336 OpCode 4 RxImm 39 OpCode 4 RxRy 336 OpCode 4 Imm 12 mov Rx, Ry add Rx, Ry sub Rx, Ry or, Rx, Ry and Rx, Ry movi Rx, Imm addi Rx, Imm subi Rx, Imm lw Rx, Ry, Imm sw Rx, Ry, Imm bez Rx, Ry, Imm jump Imm

6. ARM Pipeline Instruction Cache Fetch Decode Rename Date Cache Write Back Execute Retire PC[15:0] Inst[15:0] VInst[15:0] Op[3:0] LDst[3:0] LSrc[3:0] Imm[11:0] Op[3:0] PDst[3:0] SrcVal1[15:0 ] SrcVal2[15:0] Imm[11:0] DataIn[15:0] PDst[3:0] Addr[15:0] ReadWrite# ALU0PDst[3:0] ALU0Res[15:0] ALU1PDst[3:0] ALU1Res[15:0] MemPDst[3:0] DataOut[15:0] LDst[3:0] Val15:0] Op[3:0] PDst[3:0] SrcVal1[15:0 ] SrcVal2[15:0] Imm[11:0] BranchDecision Out Of Order

7. Out-Of-Order Engine ROB RRF RAT RS0RS1 ALU0ALU1 DATA CACHE BranchDecision to IFU Inst from ID In Order Out of Order branches non-mem inst mem inst non-branch inst

8. Hardware Requirements Gidel PROC20K card comprising: –Altera APEX 20K FPGA (type EP20K400) –2*32MB SDRAM –Integrated PCI interface –RS232 port Software Requirements Altera SignalTap2 embedded logic analyzer ARM assembler

9. Timeline 28/12/03 (mid semester report): –Asynchronous simulation of IFU+ID based on Balsa code. –Synthesis of IFU+ID pending arrival of debug software. –Detailed translation of uarch to asynchronous enviornment (handshaking, arbitration protocols). 4/3/04 (final report, first semester): –Asynchronous simulation of a complete data-path flow through the pipeline: mov R0, 1 add R0, 1