1. 1 COMP541 State Machines Montek Singh Feb 6, 2007

2. 2Topics  How to design machines that go through a sequence of events  Basically, close this loop:

3. 3 Representation of Sequential Circuits  Earlier we learned how to specify combinational circuits Truth tables, Boolean equations, … Truth tables, Boolean equations, …  Now extend to synchronous sequential circuits Include time Include time Use ‘state tables’ and ‘state diagrams’ Use ‘state tables’ and ‘state diagrams’

4. 4 Input Equations  Can describe inputs to FF with logic equations

5. 5 Time is Implied  Note that last circuit used the Previous state to determine next state Previous state to determine next state State and inputs to determine outputs State and inputs to determine outputs  Synchronous circuit So timing is discrete So timing is discrete When are transitions? When are transitions?

6. 6 State Table  Just truth table with state added

7. 7 Another Table  Same info, different layout style

8. 8 Sequential Circuit Types  Moore model – outputs depend on states  Mealy model – outputs also depend on inputs

9. 9 State Diagram  Alternative representation for state table  Moore: State/Output Inputs

10. 10 Mealy Model  Output depends on input and state Input/Output

11. 11 State Table vs. Diagram  Same information  Table is perhaps easier to fill in from description  Diagram is perhaps easier to understand You can label states with English description You can label states with English description

12. 12 Design Procedure  Take problem description and refine it into a state table or diagram  Assign codes to the states  Derive Boolean equations and implement Or, write Verilog and compile Or, write Verilog and compile  See example next class  Designing with gates and FFs more involved because you have to derive input and output functions

13. 13 Example – Sequence Recognizer  Circuit has input, X, and output, Z  Recognizes sequence 1101 on X Specifically, if X has been 110 and next bit is 1, make Z high Specifically, if X has been 110 and next bit is 1, make Z high

14. 14 How to Design States  States remember past history  Clearly must remember we’ve seen 110 when next 1 comes along  Tell me one necessary state

15. 15 Beginning State  Start state: let’s call it A  If 1 appears, move to next state B Input / Output

16. 16 Second 1  New state, C  To reach C, must have seen 11

17. 17 Next a 0  If 110 has been received, go to D  Next 1 will generate a 1 on output Z

18. 18 What else?  What happens to arrow on right?  Must go to some state.  Where?

19. 19 What Sequence?  Here we have to interpret problem  We’ve just seen 01 Is this beginning of new 1101? Is this beginning of new 1101? Or do we need to start over w/ another 1? Or do we need to start over w/ another 1?  Textbook: decides that it’s beginning (01…)

20. 20 Cover every possibility  Well, must have every possibility out of every state  In this case, just two: X = 0 or 1  You fill in other cases

21. 21 Fill in

22. 22 Answer From Book

23. 23 State Minimization  When we make state diagram, do we need all those states?  Some may be redundant  State minimization procedures can be used We won’t cover now We won’t cover now

24. 24Reading  7-1 and 7-11

25. 25Today  Simple state machines How to code them in Verilog How to code them in Verilog  Next Class More on state machine styles More on state machine styles Registers Registers Counters Counters