1. Work in Progress --- Not for Publication 1 Starting Materials Sub Sub TWG Teams

2. Work in Progress --- Not for Publication 2 Yield DRAM = exp [- D i R i A eff ] = 99% Yield - Defect Density Model Yield MPU * = exp [- D i R i T  a (CD) 2 ] = 99% Yield MPU ** = exp [- D i R i T  (CD) 2 ] = 99% * Applied to those cases where the MPU analogous cell fill factor is “K” larger than the DRAM “a” value. “K” taken as 10 at present. ** Applied to those MPU (SOI) cases where the total transistor area, unique to SOI rather than A eff, may be more appropriate (see footnotes to Tables). Defect density increases as active area decreases for constant yield * Peter Zeitzoff / Allan Alan / Neil Gayle / Huff

3. Work in Progress --- Not for Publication 3 2001 Model Calculation for Effective Active Area * For given DRAM chip area, A chip, there is memory cell area and periphery circuitry area For given DRAM chip area, A chip, there is memory cell area and periphery circuitry area For memory area, with pass transistor width/length = CD For memory area, with pass transistor width/length = CD Total memory cell transistor area (T= # transistors) is Periphery circuitry occupying remaining chip area is Total memory cell transistor area (T= # transistors) is Periphery circuitry occupying remaining chip area is Multiplying periphery circuitry area by 0.6 to get total periphery transistor area, the total effective active chip area can be written as Multiplying periphery circuitry area by 0.6 to get total periphery transistor area, the total effective active chip area can be written as * Peter Zeitzoff / Walter Class / Troy Messina / Huff