1. E ssonne N anopole September 20, 2004ALTIS Semiconductor Device Engineering team USING TCAD TO MINIMIZE PROCESS DISPERSIONS G. DUBOIS D. ANDRADE

2. E ssonne N anopole September 20, 2004ALTIS Semiconductor Device Engineering team  INTRODUCTION  CALIBRATION RESULTS  DIM PC PROCESS WINDOW SIMULATION RESULTS  OTHER PROCESS CAUSES OF VARIATION  COMBINED EFFECT OF PROCESS VARIATIONS  CONCLUSION

3. E ssonne N anopole September 20, 2004ALTIS Semiconductor Device Engineering team A - INTRODUCTION The goal is to demonstrate that TCAD could be very useful in identifying the process root causes of transistor electrical parameters dispersion, mainly Ion, Vt and Ioff.The following study was done on a 0.18µm designed gate length CMOS process.

4. E ssonne N anopole September 20, 2004ALTIS Semiconductor Device Engineering team DEVICES MENU

5. E ssonne N anopole September 20, 2004ALTIS Semiconductor Device Engineering team B - CALIBRATION  PROCESS CALIBRATION: Impurity diffusion, activation models and dislocation calibration variables were taken from INFINEON calibration work.  ELECTRICAL CALIBRATION : Mobility model has been shared with INFINEON simulation group.  RESULTS : I-V Characteristics end up very close to measurements performed on product.

6. E ssonne N anopole September 20, 2004ALTIS Semiconductor Device Engineering team

7. E ssonne N anopole September 20, 2004ALTIS Semiconductor Device Engineering team SOURCEDRAIN FET CHANNEL LENGTH

8. E ssonne N anopole September 20, 2004ALTIS Semiconductor Device Engineering team Simulation properly matches product measurements.

9. E ssonne N anopole September 20, 2004ALTIS Semiconductor Device Engineering team C – PC DIM PROCESS WINDOW SIMULATION

10. E ssonne N anopole September 20, 2004ALTIS Semiconductor Device Engineering team

11. E ssonne N anopole September 20, 2004ALTIS Semiconductor Device Engineering team

12. E ssonne N anopole September 20, 2004ALTIS Semiconductor Device Engineering team C – PC DIM PROCESS WINDOW SIMULATION  The simulation shows a good matching with « the real world ».  Halo implant tailoring allows to reduce the Ion (or Vt) spread, due to PC DIM variation, within +/- 5 %.

13. E ssonne N anopole September 20, 2004ALTIS Semiconductor Device Engineering team D - ANALYSIS OF OTHER CAUSES OF ELECTRICAL VARIATION 1° VARIATION OF EXTENSION IMPLANT DUE TO SCREEN OXIDE THICKNESS SPREAD. The extension implant being low energy, it is strongly influenced by screen oxide thickness variation…

14. E ssonne N anopole September 20, 2004ALTIS Semiconductor Device Engineering team POLY SPACER 0 REMAINING Gox + SPACER 0 on Si

15. E ssonne N anopole September 20, 2004ALTIS Semiconductor Device Engineering team TCAD simulation shows that:  A huge variation of remaining gate oxide induces a small variation of screen oxide.  Screen oxide thickness variation represents 50% of Spacer 0 (poly oxidation thickness) variation.  Consequently, the extension implant is not impacted by gate oxide, nor Spacer 0 fluctuations.

16. E ssonne N anopole September 20, 2004ALTIS Semiconductor Device Engineering team 2° VARIATION OF ANNEALS TEMPERATURE Rapid Thermal Process single wafer tools, using infra red heating systems, may present slight temperature variations inducing wafer to wafer, and within wafer, spread.

17. E ssonne N anopole September 20, 2004ALTIS Semiconductor Device Engineering team

18. E ssonne N anopole September 20, 2004ALTIS Semiconductor Device Engineering team E – COMBINED EFFECTS OF PROCESS VARIATIONS

19. E ssonne N anopole September 20, 2004ALTIS Semiconductor Device Engineering team

20. E ssonne N anopole September 20, 2004ALTIS Semiconductor Device Engineering team TCAD simulation consists in a very efficient support for manufacturing engineers. It indeed provides an accurate sizing of the different processes effect. Only considering PC dim & T° anneal variations induces 85% of the devices electrical parameters total spread. Those two components are the first order root causes of the total device electrical variation. F – CONCLUSION