1. 26 February 2002ATLAS Muon Electronics Meeting1 MROD: the MDT Read Out Driver Status of MROD-1 Prototype Adriaan König University of Nijmegen

2. 26 February 2002ATLAS Muon Electronics Meeting2 Contents System Overview MROD-1 Prototype Status Plans Names

3. 26 February 2002ATLAS Muon Electronics Meeting3 System Overview 6 x MROD S-Link to ROB TDC 1 TDC 18 CSM 18 x TDC 1 TDC 18 CSM 18 x Chamber Tower CSM-Link

4. 26 February 2002ATLAS Muon Electronics Meeting4 CSM-MUX Functionality Serial to Parallel & Clock Domain Separator 40 Mbit/s Data/Strobe from TDC 18 x Serial to Parallel & Clock Domain Separator 40 Mbit/s Data/Strobe from TDC Separator (CSM-Link)  1 Gbit/s 1 Start bit 32 Data bits 1 Parity bit 1 Stop bit 35 bits @ 25 ns = 875 ns 1 Separator word (S) 18 TDC data words 19 words in 875 ns  87 MB/s S 1 18 CSM-MUX

5. 26 February 2002ATLAS Muon Electronics Meeting5 TDC0, word 1 TDC2, word 4 TDC3, word 2 TDC0, word 1 TDC1, word 3 TDC2, word 5 TDC3, word 3 TDC3, word 0TDC2, word 0TDC1, word 0 TDC1, word 1 TDC1, word 2 TDC2, word 1 TDC2, word 2 TDC2, word 3 TDC3, word 1 Build events in a partitioned memory from TDC data fragments (tdc 1) 000…000 Separator word Skip (do not store) Check (do not store) MROD Functionality time (tdc 0) 000…000 TDC0, word 0

6. 26 February 2002ATLAS Muon Electronics Meeting6 MROD Throughput MROD MROD-in MROD-out Average 5 hits per TDC + header + trailer = 7 words/event Per tower of 6 chambers max. 88 TDCs * 7  600 words/event (= 2.4 kB/event) Worst case est.: @ 100 kHz L1A rate  240 MB/s per MROD Calculation based on actual tower layout (J.Chapman): max. rate < 60 MB/s per MROD CSM-Link S-Link CSM-Link MROD-in

7. 26 February 2002ATLAS Muon Electronics Meeting7 MROD Form Factor 9 U VME board (single slot), 6 CSM Inputs, 1 S-Link Output Optionally 2 extra CSM Inputs with “extension” board to accommodate some special towers with > 6 chambers CSM Input Interfaces integrated on main board 1 MROD Crate (Sub rack) contains: 12 MRODs (12  Segments) Up to 4 MROD extension boards 1 Crate Master with Ethernet Interface (DetDAQ) 1 TIM: TTC-Rx Interface Module (incl. ROD Busy) @ 192 towers: 192/12 = 16 MROD Crates (1 per  Sector)

8. 26 February 2002ATLAS Muon Electronics Meeting8 MROD Crate LDAQMROD … total... 12 x 6 CSMs TTCrx Interface Module ROD Busy ROB DAQ / DCS VME-bus One MROD Crate services 12 towers (e.g. one full  sector). In total 16 crates will be required for all MDT chambers. Some MRODs may have 7 or 8 input links via “slave” MROD input cards. From TTC system “TIM-bus” Network

9. 26 February 2002ATLAS Muon Electronics Meeting9 MROD -1 Prototype Memory SHARC FPGA SHARC (2x) Memory FPGA 3x ( in total ) VME64x TTC Interface Memory SHARC FPGA Memory FPGA Sharc Links

10. 26 February 2002ATLAS Muon Electronics Meeting10 MROD-1 Prototype Form Factor 9 U VME boards, 2 units wide 1 S-Link output on daughter board 6 S-Link inputs on daughter boards SHARC II (ADSP21160) DSPs: (3 for input, 2 for output processing) Altera APEX FPGAs, 200k gates TIM bus over special P3 back plane VME64x interface Motherboard Output Input S-Link daughter boards

11. 26 February 2002ATLAS Muon Electronics Meeting11 MROD-1 Prototype Status MROD-1 module exists. FPGA code has been tested, debugged and verified. Quite a few problems with SHARC-II DSPs: work-arounds being implemented; testing continues. More MROD-1 modules will be available soon. More software tools are being developed.

12. 26 February 2002ATLAS Muon Electronics Meeting12 MROD-in board

13. 26 February 2002ATLAS Muon Electronics Meeting13 MROD-out board

14. 26 February 2002ATLAS Muon Electronics Meeting14 MROD-in power-up modification

15. 26 February 2002ATLAS Muon Electronics Meeting15 Detail power-up modification

16. 26 February 2002ATLAS Muon Electronics Meeting16 MROD-1 Prototype Plans Read out of BOL chambers in NIKHEF cosmic ray test stand with TDC32 chips and special CSM-MUX. Read out of BOL test stand chamber @ NIKHEF with ASD mezzanine cards through CSM adapter box and special CSM-MUX. Direct read out of ASD mezzanine cards with “final” CSM and MROD-1 with CSM-Link interface (“next” MROD-1 prototype).

17. 26 February 2002ATLAS Muon Electronics Meeting17 Next MROD-1 Prototype Same 9 U VME board, 2 units wide 1 S-Link output on daughter board 6 CSM-Link inputs on daughter boards Reprogramming of MROD-in FPGAs Motherboard Output Input CSM-Link daughter boards S-Link daughter board

18. 26 February 2002ATLAS Muon Electronics Meeting18 MROD Names (NIKHEF and Univ.of Nijmegen) Marcello Barisonzi Henk Boterenbrood Jasper Hendriks Peter Jansweijer Gerard Kieft Adriaan König Jos Vermeulen Thei Wijnen