1. Encryption Transaction with 3DES Team W2 Yervant Dermenjian (W21) Taewan Kim (W22) Evan Mengstab(W23) Xiaochun Zhu(W24) Objective: To implement a secure credit card transaction using 3DES encryption using Kerberos-style authentication. Current Stage: Full Chip LVS 03/24/2004 Design Manager: Rebecca Miller

2. Current Status  Design Proposal (100% done)  Architecture Proposal (100% done)  Size Estimate and Floor Plan (100% done)  Full-chip Transistor-level Schematic (100% done)  Component Layout & Simulation (100% done) Basic components Basic components  To be done Layout of larger blocks Layout of larger blocks Component Simulation Component Simulation Full Chip Layout (100% done) Full Chip Layout (100% done) Spice simulation of the entire chip Spice simulation of the entire chip

3. Schematic Reverification

4. Final Schematic

5. LVS Output

7. Poly & Active

8. Metal 1

9. Metal 2

10. Metal 3

11. Metal 4

12. Final Layout Input Latch Initial Permutation Barrel Shifting Key Register Barrel Shifting Initial Permutation Final Permutation Key Register XOR Expand Permutation P Permutation S BOX ROM and Decoders Program Control Transistors: 13749 Area: 378.8μm x 366.8 μm

13. Dimensions 366.8 um x 378.8 um = 138,943.8 um^2 366.8 um x 378.8 um = 138,943.8 um^2 Transistor Count = 13749 Transistor Count = 13749 Transistor Density = 0.1 Transistor Density = 0.1 Aspect Ratio = 1 : 1.03 Aspect Ratio = 1 : 1.03 Estimated Clock Speed = 200Mhz Estimated Clock Speed = 200Mhz

14. Questions ?