1. S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 22: Material Review Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley – Rabaey/Pearson]

2. S. Reda EN160 SP’07 Impact of doping on silicon resistivity dope with phosphorous or arsenic  n-type dope with boron  p-type silicon 4.995  10 22 atoms in cm 3 Resistivity 3.2  10 5 Ωcm 1 atom in billion  88.6 Ωcm 1 atom in million  0.114 Ωcm 1 atom in thousand  0.00174 Ωcm 1 atom in billion  266.14 Ωcm 1 atom in million  0.344 Ωcm 1 atom in thousand  0.00233 Ωcm  Electrons are more mobile/faster than holes

3. S. Reda EN160 SP’07 Use P and N material to make diodes and transistors and gates n p A B Al One-dimensional representation

4. S. Reda EN160 SP’07 Layouts versus stick diagrams

5. S. Reda EN160 SP’07 IC manufacturing Spin resist Expose (using mask) Develop resist ACTION (e.g., implant) Remove Resist

6. S. Reda EN160 SP’07 The MOS transistor has three regions of operation Cut off V gs < V t Linear (resistor): V gs > V t & V ds < V gs -V t Current α V ds Saturation: V gs > V t and V ds ≥ V gs -V t Current is independent of V ds NMOS transistor, 0.25um, Ld = 10um, W/L = 1.5, VDD = 2.5V, VT = 0.4V

7. S. Reda EN160 SP’07 Non-ideal Shockley vs actual operation Channel length modulation: Increasing Vds decreases channel length increases current Velocity saturation: At high electric field, drift velocity rolls off due to carrier scattering Temperature dependency

8. S. Reda EN160 SP’07 Inverter voltage transfer characteristics A B C E D

9. S. Reda EN160 SP’07 CMOS inverter noise margins desired regions of operation V in V out

10. S. Reda EN160 SP’07 Simple RC delay models Use equivalent circuits for MOS transistors –Ideal switch + capacitance and ON resistance –Unit nMOS has resistance R, capacitance C –Unit pMOS has resistance 2R, capacitance C Capacitance proportional to width Resistance inversely proportional to width

11. S. Reda EN160 SP’07 Elmore delay model ON transistors look like resistors Pullup or pulldown network modeled as RC ladder Elmore delay of RC ladder

12. S. Reda EN160 SP’07 Logical effort to calculate gate delay g: logical effort = ratio between input capacitance of the gate to that of an inverter than would deliver the same current h: electric effort = ratio between load capacitance and the gate input capacitance (sometimes called fanout) p: parasitic delay represents delay of gate driving no load set by internal parasitic capacitance

13. S. Reda EN160 SP’07 Effort of Multistage logic networks Logical effort generalizes to multistage networks Path Logical Effort Path Electrical Effort Branching factor Path Effort F=GBH

14. S. Reda EN160 SP’07 Optimization using logical effort models Delay of multi-stage network is minimized when each stage bears the same effort Optimal number of stages

15. S. Reda EN160 SP’07 Power Dynamic Short circuit power (dynamic) Static (leakage) Techniques to reduce power: clock gating, multiple Vdd, multiple Vt, temperature,

16. S. Reda EN160 SP’07 Interconnects They have resistance and capacitance → contribute to delay and dynamic power Distributed vs lumped Elmore delay model How to calculate delay (gate + wires)?

17. S. Reda EN160 SP’07 Interconnects Coupling capacitance introduces cross talk which depends on the switching activity of the neighboring wires. Cross talk increases delay and causes noise Solutions to interconnect problems 1. Width, Spacing, Layer 2. Shielding 3. Repeater insertion 4. Wire staggering and differential signaling 5. Buffer insertion (what are the locations/optimal number?) 6. Staggering and differential signaling

18. S. Reda EN160 SP’07 Implications of ideal device scaling devices interconnects

19. S. Reda EN160 SP’07 Logic families Asymmetric gates (favors one input) Skewed gates (favors one transition) How to calculate logical effort? Families to get rid of some of static CMOS problems: help in one way, introduces another problem Pseudo-NMOS (ratioed circuits) Cascode Voltage Switch Level CPTL PTL domino

20. S. Reda EN160 SP’07 Circuit Design Pitfalls Design in corners make sure you have enough margins variations