1. Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.edu ECE 491 - Senior Design I Lecture 15 - Handshaking Fall 2007 Quiz Friday 10/19: Ethernet Paper Reading: “How to Read a Technical Paper”, Ethernet Paper

2. ECE 491 Fall 2007Lecture 15 - Handshaking2 Where we are  Last Time:  Synchronizers and Metastability  Detailed Design  Today:  Handshaking for Communicating State Machines  Reference:  C. Cummings, “Synthesis and Scripting Techniques for Multi- Asynchronous Clock Designs”, SNUG 2002, http://www.sunburst-design.com/papers/CummingsSNUG2001SJ_AsyncClk_rev1_1.pdf

3. ECE 491 Fall 2007Lecture 15 - Handshaking3 Goals of Handshaking  Reliably pass control information between systems  Reliably pass data between interacting systems  Systems may be driven by different clocks! SR SR DO_CMD DATA clk1clk2 clk1clk2

4. ECE 491 Fall 2007Lecture 15 - Handshaking4 Handshaking  Basic Idea:  Receiver performs “action” at request of sender Transfer data Perform a sub-computation  Want action to be performed once for each request  Types of Handshaking  1-way  2-way  3-way  4-way (fully interlocked)

5. ECE 491 Fall 2007Lecture 15 - Handshaking5 1-Way Handshake  R waits for CMD before starting action  S asserts CMD to start action CMD SR SCMD S1 SN-2 SN-1 SN SN-1 RWAIT CMD CLK S State R State SN RWAIT SCMD RWAIT S1 R1 S2 R2 CMD RWAIT R1 RM T F

6. ECE 491 Fall 2007Lecture 15 - Handshaking6 1-way Handshake: Observations  Not reliable - why?  Receiver can “miss” assertion of CMD if it isn’t in RWAIT  Receiver may see assertion of CMD twice if it runs on a faster clock than sender

7. ECE 491 Fall 2007Lecture 15 - Handshaking7 2-Way Handshake 1.Sender asserts CMD and waits for ACK before continuing 2.Receiver waits for CMD and then asserts ACK CMD SR ACK CMD SCMD F SN-2 SN-1 SN ACK CMD RWAIT R1 RM F T ACK SN-1 RWAIT SN RWAIT SCMD RWAIT SCMD R1 S1 R2 CMD CLK S State R State ACK

8. ECE 491 Fall 2007Lecture 15 - Handshaking8 2 Way Handshake - Observations  Reliable if S and R use same clock  Not reliable if S and R use different clocks  R could see CMD twice if R faster than S  S could see ACK twice if S faster than R

9. ECE 491 Fall 2007Lecture 15 - Handshaking9 3-Way Handshake 1.Sender asserts CMD and waits for ACK before continuing 2.Receiver waits for CMD and then asserts ACK 3.Receiver waits for CMD=0 before continuing CMD SR ACK CMD SCMD F SN-2 SN ACK CMD RW1 RW2 R1 F T ACK SN RWAIT SCMD RW1 CMD CLK S State R State ACK T T F CMD CMD’ SCMD RW2 S1 S2 R1

10. ECE 491 Fall 2007Lecture 15 - Handshaking10 3-Way Handshake - Comments  Use in some asynchronous bus interfaces  Not reliable if S is faster than R (see ACK twice)

11. ECE 491 Fall 2007Lecture 15 - Handshaking11 4-Way Handshake (Fully Interlocked) 1.Sender asserts CMD and waits for ACK before continuing 2.Receiver waits for CMD and then asserts ACK 3.Receiver waits for CMD=0 before continuing 4. Sender waits for ACK=0 before continuing CMD SR ACK RW1 RW2 SC1 RW1 CMD CLK S State R State ACK CMD R1 F T ACK T F CMD CMD’ SC1 RW2 SC2 R1 CMD SC1 F SN ACK T SC2 ACK T ACK’

12. ECE 491 Fall 2007Lecture 15 - Handshaking12 4-Way Handshaking  Works under all circumstances  Still need synchronizers if clocks are different! clk1 clk2 SR CMD ACK clk1 clk2

13. ECE 491 Fall 2007Lecture 15 - Handshaking13 Handshaking with Multiple Clocks  Treat signals passing between S and R as asynchronous!  Important: never try to handshake on multiple bits  Use synchronizers when crossing clock domains

14. ECE 491 Fall 2007Lecture 15 - Handshaking14 Handshaking with Multiple Clocks  CMD, ACK must be synchronized!  Penalty: even more latency! S R CMD ACK.s1 DQDQ QDQD CMD.s2 ACK clk1clk2

15. ECE 491 Fall 2007Lecture 15 - Handshaking15 Alternative to Handshaking: FIFOs  FIFO = First In / First Out Buffer  S writes data once each clock cycle unless FULL  R reads data once every clock cycle unless EMPTY SR SCLK FULL RCLK EMPTY

16. ECE 491 Fall 2007Lecture 15 - Handshaking16 FIFO Implementation - Software  Head pointer - marks where to add data  Tail pointer - marks where to remove data  Exceptional conditions: FULL, EMPTY Write Pointer (Head) FULL Read Pointer (Tail) EMPTY 9 7 5 Array (RAM) 0x0 0x7

17. ECE 491 Fall 2007Lecture 15 - Handshaking17 FIFO Implementation - Hardware Dual-Port RAM WDATA WADDR WR RDATA RADDR Write Logic Read Logic CLK2CLK1 FULL DATA EMPTY DATA  Q: How do we calculate FULL & EMPTY? TAILHEAD

18. ECE 491 Fall 2007Lecture 15 - Handshaking18 FIFO Implementation - Hardware Dual-Port RAM WDATA WADDR WR RDATA RADDR Write Logic Read Logic CLK2CLK1 FULL DATA EMPTY DATA  Q: How do we calculate FULL & EMPTY?  A: Must compare head & tail pointers TAILHEAD

19. ECE 491 Fall 2007Lecture 15 - Handshaking19 FIFO Implementation - Hardware  Problem:  Read logic (clk1) needs to see Tail pointer (clk2)  Write logic (clk2) needs to see the Head pointer (clk1)  Proposed Solution:  Synchronize Head, Tail  Problem again! Multiple bits in Head, Tail  Synchronization won’t work on multiple bits!  Complete Solution:  Use Gray Code for Head, Tail (only 1 bit changes at a time!)  Translate to/from binary internally

20. ECE 491 Fall 2007Lecture 15 - Handshaking20 Coming Up  Manchester Transmitter Design  Manchester Receiver Design  Intellectual Property