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1.ATLAS and ID 2.SCT 3.Commissioning 4.Integration 5.Latest Runs 6.Conclusions Commissioning the ATLAS Silicon Microstrip Tracker IPRD08 - Siena Jose E.

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Presentation on theme: "1.ATLAS and ID 2.SCT 3.Commissioning 4.Integration 5.Latest Runs 6.Conclusions Commissioning the ATLAS Silicon Microstrip Tracker IPRD08 - Siena Jose E."— Presentation transcript:

1 1.ATLAS and ID 2.SCT 3.Commissioning 4.Integration 5.Latest Runs 6.Conclusions Commissioning the ATLAS Silicon Microstrip Tracker IPRD08 - Siena Jose E. Garcia Université de Genève for the Atlas SCT collaboration

2 ATLAS Detector 2 1.ATLAS and ID 2.SCT 3.Commissioning 4.Integration 5.Latest Runs 6.Conclusions Jose E. Garcia IPRD08 - Siena ATLAS is being assembled to exploit the 14TeV pp collisions at the LHC The Inner Detector forms the heart of the ATLAS experiment. The closest to the interaction point. Pixel Detector Semiconductor Tracker (SCT) Transition Radiation Detector (TRT)

3 Semi-Conductor Tracker 3 Jose E. Garcia IPRD08 - Siena 61 m 2 of silicon with 6.2 million readout channels 4088 silicon modules arranged to form 4 Barrels and 9+9 Disks Barrels : 2112 modules with acceptance |  | < 1.1 to 1.4 Endcaps : 1976 modules with acceptance 1.1 to 1.4 <|  | < 2.5 Space point resolution r  ~17  m / Z ~ 580  m (23  m strip resolution) Radiation hard: tested to 2x10 14 1-MeV neutron equivalent /cm 2 Material: 3% X 0 per layer ( = 0) 1.ATLAS and ID 2.SCT 3.Commissioning 4.Integration 5.Latest Runs 6.Conclusions

4 Silicon Modules 4 Jose E. Garcia IPRD08 - Siena Back-to-back sensors, glued to highly thermally conductive substrates for mechanical stability and sensor cooling 40mrad stereo angle between sensors 1536 channels (768 on each side) Optical communication 5.6W/module (adding ~1W per sensor after 10 years LHC) Cooled to -25 o C to limit sensor radiation damage and -8 o C ambient temperature. up to 500V sensor bias 2112 Barrel modules one module type 1976 EndCap modules 4 module types 1.ATLAS and ID 2.SCT 3.Commissioning 4.Integration 5.Latest Runs 6.Conclusions

5 Front End Electronics 5 Jose E. Garcia IPRD08 - Siena 128 channel ASIC with binary architecture Radiation-hard DMILL technology 12 chips per module (6 each side) glued to hybrid (Cu/polyimide flex circuit) 40MHz (25ns) clock 20ns front end shaping time Redundancy scheme (chips, link, TTC) 1.ATLAS and ID 2.SCT 3.Commissioning 4.Integration 5.Latest Runs 6.Conclusions

6 Assembly Sites 6 Jose E. Garcia IPRD08 - Siena 4 Assembly Sites Oxford - Barrel Nikhef - EndCap A Liverpool - EndCap C SR1 at CERN 1.ATLAS and ID 2.SCT 3.Commissioning 4.Integration 5.Latest Runs 6.Conclusions

7 Installation Timeline 7 Jose E. Garcia IPRD08 - Siena 2006 Quarter 1 Quarter 2 Quarter 3 Quarter 4 2007 Quarter 1 Quarter 2 Quarter 3 Quarter 4 2008 Quarter 1 Quarter 2 Quarter 3 Quarter 4 Barrel in Pit EndCaps in Pit ID sealed ID operational in Atlas Cooling Issues 3 ID compressors failed 100 kg of C3F8 lost and 900 contaminated Cooling plant cleaned up and broken parts replaced Fortunately detector not affected Measures have been taken to prevent this to happen again Test Module connectivity and performance comparing with surface data 1.ATLAS and ID 2.SCT 3.Commissioning 4.Integration 5.Latest Runs 6.Conclusions Pixels in Pit

8 Commissioning Tests 8 Jose E. Garcia IPRD08 - Siena Electrical Connections Check LV arrives at modules: V DD, V CC, I PIN, I VCSEL HV current voltage scan Check temperature readings Optical Connections P-i-n current checks Light from fiber data measured at Redaout Driver (ROD) Check fiber connection and correct module mapping Calibration Tests Digital and Analogue functionality tested Gain curve, Noisy/Dead channel map Noise occupancy Tests Cosmic Tests Milestone 6 (M6) : Global commissioning run with ATLAS 1.ATLAS and ID 2.SCT 3.Commissioning 4.Integration 5.Latest Runs 6.Conclusions Combined SCT and TRT track.

9 Atlas Integration 9 Jose E. Garcia IPRD08 - Siena Calibration and configuration changes are being made to improve performance. Some modules were removed from due to readout issues. They will be back in once they are properly adjusted. Approximate numbers: – Barrel: 99.6% modules – EndCaps (*): 97.8% modules (*2 out of 72 cooling loops off, partially recoverable during shutdown) Around 97% configuration for stable readout in ATLAS 1.ATLAS and ID 2.SCT 3.Commissioning 4.Integration 5.Latest Runs 6.Conclusions Standalone calibration was performed up to the first week of September. From then SCT has been included in the Atlas data taking – Full Barrel and Endcap ROD readout – Athena and ROS Level Monitoring – Data Quality Monitoring Since middle of August cooling is back and running stably for the detectors. SCT running fully powered since end August

10 Noise Occupancy 10 Jose E. Garcia IPRD08 - Siena 1.ATLAS and ID 2.SCT 3.Commissioning 4.Integration 5.Latest Runs 6.Conclusions Barrel Noise Occupancy at 150 V measured ~4.4 x 10 -5 Outer/middle NO of ~ 5 x10 -5 Inner type modules much lower due to short strip length Values in agreement to measurements from production, integration and installation.

11 Broken TX fibre or dead PIN Clock and control from neighbouring module Broken TX fibre or dead PIN Clock and control from neighbouring module Current issue: TTC link 11 Jose E. Garcia IPRD08 - Siena Some SCT channels generate no pin current (TX). Suspect ESD damage. RX Ch TX Ch ROD BOC DATA TTC Currently affected around 2.5 % of the modules o Currently we are using redundancy whenever possible (this is not possible where two adjacent modules have zero pin current). o If a few channels in a specific TX plugin are lost, it will be needed to change them. o Plugins can be replaced at the USA15. Newly manufactured plugins are being tested. 1.ATLAS and ID 2.SCT 3.Commissioning 4.Integration 5.Latest Runs 6.Conclusions Broken TX fibre or dead PIN Clock and control from neighboring module

12 Timing In with ATLAS 12 Jose E. Garcia IPRD08 - Siena Apply global trigger delay offset on top of the 4088 individual delays, and scan offset to look for increase in number of coincidental hits, increasing the number of space-points and tracks. Reading 3 bunch crossings (3 x 25 ns clock cycles). Scans were done and SCT was timed in using cosmics before first beam and continued after LATER (with beam!): When roughly timed in, start fine delay (steps of 280ps) to tune relative bin occupancies and optimise hit efficiency. Fine scan delay scan with different offsets for each module 1.ATLAS and ID 2.SCT 3.Commissioning 4.Integration 5.Latest Runs 6.Conclusions 01X

13 First Beam (10 th Sept) 13 Jose E. Garcia IPRD08 - Siena 1.ATLAS and ID 2.SCT 3.Commissioning 4.Integration 5.Latest Runs 6.Conclusions SCT EndCaps at 20 V during the first beam Many tracks and space-points seen during the circulating beam

14 Combined Tracks: SCT + Pixels 14 Jose E. Garcia IPRD08 - Siena 1.ATLAS and ID 2.SCT 3.Commissioning 4.Integration 5.Latest Runs 6.Conclusions Data taking is ongoing 24/7 with the rest of the sub-systems. First tracks seen with hits in pixels and SCT combined

15 The residuals for the SCT barrel show a behaviour similar to the M6 results. Alignment with Last Cosmics Data 15 Jose E. Garcia IPRD08 - Siena 1.ATLAS and ID 2.SCT 3.Commissioning 4.Integration 5.Latest Runs 6.Conclusions SCT Level 1 Barrel EndCap Level 2 Barrel layers EndCap disks Level 3 Barrel modules EndCap modules Hits on tracks for barrel layers The residuals for the SCT barrel show a behavior similar to the M6 results.

16 Conclusions 16 Jose E. Garcia IPRD08 - Siena 1.ATLAS and ID 2.SCT 3.Commissioning 4.Integration 5.Latest Runs 6.Conclusions SCT running fully powered since beginning of September with 97% configuration for stable readout in ATLAS after the first round of readout adjustments. Integrated the full SCT into ATLAS combined partition Observed first beam and used beam splashes to get first timing (on endcaps) Currently ongoing cosmics runs for: – Timing studies – Alignment – DAQ, DCS and Monitoring tuning up – Improvement on module calibration

17 Backup Slides 17 Jose E. Garcia IPRD08 - Siena 1.ATLAS and ID 2.SCT 3.Commissioning 4.Integration 5.Latest Runs 6.Conclusions 7.Backup

18 Timing In 18 Jose E. Garcia IPRD08 - Siena BOC coarse delay Up to 32 clock cycles BOC fine delay up to 35ns in 280ps steps … x48 ROD Trig ROD Crate FINE Fibres to modules Compensate for different propagation delays of C&C from BOC to module (which varies from 380ns to 446ns) 4088 individual delays from 0 to 66ns 1.ATLAS and ID 2.SCT 3.Commissioning 4.Integration 5.Latest Runs 6.Conclusions 7.Backup

19 Optical Communication 19 Jose E. Garcia IPRD08 - Siena 1.ATLAS and ID 2.SCT 3.Commissioning 4.Integration 5.Latest Runs 6.Conclusions 7.Backup


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