1. Toward Performance-Driven Reduction of the Cost of RET-Based Lithography Control Dennis Sylvester (dennis@eecs.umich.edu), Jie Yang (Univ. of Michigan, Ann Arbor) Puneet Gupta, Andrew B. Kahng (UC San Diego)

2. Outline Trends in Mask Cost Design for Value MinCorr: The Cost of Correction Problem Generic Cost of Correction Methodology MinCorr: Parallels to Gate Sizing Experiments and Results Conclusions and Ongoing Work

3. Trends in Mask Cost “$1M mask set” in 100nm, but average only 500 wafers per set

4. Trends in Mask Cost.. RETs increase mask feature complexities and hence mask costs The average mask set produces only 570 wafers  amortization of mask cost is difficult Mask writers work equally hard to perfect critical and non-critical shapes; errors found in either during mask inspection will cause the mask to be discarded

5. Outline Trends in Mask Cost Design for Value MinCorr: The Cost of Correction Problem Generic Cost of Correction Methodology MinCorr: Parallels to Gate Sizing Experiments and Results Conclusions and Ongoing Work

6. Design for Value Prohibitive mask costs motivate a need for Design for Value (DFV) methodologies Achieve required parametric yield Minimize cost incurred Multiple selling points f i with associated value v(f) and yield y(f)  Total Design Value =  y(f)*v(f) Probabilistic optimization regime

7. DFV: At Process Level Inject concept of function into mask flow Selective OPC Various levels of OPC depending on timing and yield criticality of features Obtain desired level of parametric yield

8. Outline Trends in Mask Cost Design for Value MinCorr: The Cost of Correction Problem Generic Cost of Correction Methodology MinCorr: Parallels to Gate Sizing Experiments and Results Conclusions and Ongoing Work

9. MinCorr: The Cost of Correction Problem  Many features in layout are not timing critical  more process variation may be tolerable for them  Less-aggressive OPC  lower costs (reduced figure counts, shorter mask write times, higher yields)  Printability of the design  a certain minimum level of OPC is required

10. MinCorr: The Cost of Correction Problem..  Define the selling point as the circuit delay which achieves 99% parametric yield The MinCorr problem seeks a level of correction for each layout feature such that a prescribed selling point delay is attained with minimum total cost of corrections.

11. Outline Trends in Mask Cost Design for Value MinCorr: The Cost of Correction Problem Generic Cost of Correction Methodology MinCorr: Parallels to Gate Sizing Experiments and Results Conclusions and Ongoing Work

12. Generic Cost of Correction Methodology Statistical STA provides PDFs of arrival times at all nodes Given target selling point delay   slack at all POs  correct/decorrect gates Assume variation aware library models (for delay) are available

13. Outline Trends in Mask Cost Design for Value MinCorr: The Cost of Correction Problem Generic Cost of Correction Methodology MinCorr: Parallels to Gate Sizing Experiments and Results Conclusions and Ongoing Work

14. MinCorr: Parallels to Gate Sizing Statistical STA currently has runtime and scalability issues Assume Perfect correlation of variation along all paths (spatial correlation…) Gaussian-ness of distributions prevails Resulting linearity allows propagation of (  +3  ) or 99% (selling point) delay to primary outputs using standard Static Timing Analysis (STA) tools

15. MinCorr: Parallels to Gate Sizing..  Use off-the-shelf synthesis tool, along with yield library similar to timing libraries (e.g.,.lib) to perform OPC “sizing” operation Gate Sizing  MinCorr Cell Area  Cost of correction Nominal Delay  Delay (  +k  ) Cycle Time  Selling point delay Die Area  Total cost of OPC

16. MinCorr: Yield Aware Library Characterization  Mask cost is assumed proportional to number of layout features  Monte-Carlo simulations, coupled with linear interpolation, are used to estimate delay variance given the CD variation  We generate a library similar to Synopsys.lib with (  +3  ) delay values for various output loads

17. Outline Trends in Mask Cost Design for Value MinCorr: The Cost of Correction Problem Generic Cost of Correction Methodology MinCorr: Parallels to Gate Sizing Experiments and Results Conclusions and Ongoing Work

18. Experiments and Results  Synopsys Design Compiler used as the synthesis tool to perform “gate sizing”  Figure counts, critical dimension (CD) variations derived from Numerical Technologies OPC tool

19. Experiments and Results Three levels of OPC considered Input slew dependence ignored Interconnect variation ignored Type of OPC Ldrawn (nm) 3  of Ldrawn Figure Count Delay ( ,  ) for NAND2X1 Aggressive1305%5X(60.7, 7.03) Medium1306.5%4X(60.7, 7.47) No OPC13010%1X(60.7, 8.79) Sample Result of Library Generation

20. Experiments and Results  Small (4%) selling point delay variation between max- and min-corrected versions of design  Sizing-based optimization achieves 60- 79% reduction in OPC cost without sacrificing parametric yield

21. Experiments and Results 4 combinational testcases ranging from 1600 to 9400 gates DesignNormalized CostNormalized Selling Point Delay alu1285.0 (Aggressive OPC)0.9644 4.0 (Medium OPC)0.9739 1.0 (No OPC)1.0000 1.06570.9644 1.01190.9976 Sample results on 9410 gate testcase alu128

22. Outline Trends in Mask Cost Design for Value MinCorr: The Cost of Correction Problem Generic Cost of Correction Methodology MinCorr: Parallels to Gate Sizing Experiments and Results Conclusions and Ongoing Work

23. Conclusions  Function-aware OPC can reduce total cost of OPC while still meeting cycle time and yield constraints  Can modify conventional performance optimization methods to solve the MinCorr problem;  We use an off-the-shelf synthesis tool to achieve up to 79% cost reduction compared to aggressive OPC, without increasing selling point delay

24. Ongoing Work  Statistical static timing analysis based correction flow  use SSTA for validation rather than for core optimization due to runtime and scalability issues  Applying selective OPC at granularities other than gate-level (incl. radius of influence effects)  Alternative MinCorr solution approaches based on transistor sizing and cost based delay budgeting methods  Including interconnect variation in the analysis  Making the yield library input transition time aware