1. Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.edu ECE 425 - VLSI Circuit Design Lecture 10 - Combinational Logic (cont’d) Low Power Logic; RC Network Delays Spring 2007

2. ECE 425 Spring 2007Lecture 10 - Comb. Logic2 Announcements  Homework Due Mon. Mar. 5  3-1, 3-4, 3-6, 3-7, 3-14, 3-16  Reading  3.1-3.7  Exam 1: Scheduled for Wed. March 7

3. ECE 425 Spring 2007Lecture 10 - Comb. Logic3 Where we are  Last Time  Power Consumption  Parasitics and Performance  Driving Large Loads  Alternative Logic Families  Today  Body Effect  Techniques for Reducing Power Consumption  Delay in long wires

4. ECE 425 Spring 2007Lecture 10 - Comb. Logic4 Body Effect  We’ve used fixed values for V tp, V tn, BUT  This is true only if source/substrate voltage V sb =0  Not always the case when transistors are in series  Increasing V sb  increases width of depletion layer  raises the threshold voltage V t  Example (p. 56): if V sb =5V, ∆V t =0.16V (24% of V t )

5. ECE 425 Spring 2007Lecture 10 - Comb. Logic5 Result of Body Effect: Increased Delay  Consider n-transistors in series:  T1 has higher V t while C1 charged  T1 turns on more slowly  C L discharges more slowly  Delay (fall time) increases!  What to do?  Attempt to reduce parasitic C 1 - ”internal node capacitance”  Place “earliest-arriving” gate inputs near Gnd (V DD, for p-transistors)  Place “latest-arriving” gate inputs near output

6. ECE 425 Spring 2007Lecture 10 - Comb. Logic6 More Techniques for Saving Power  Reduce VDD  Reducing VDD increases delay!  Common tradeoff: add extra logic e.g. parallel adders (architecture-driven voltage scaling)  Multiple Power Supplies (level translation an issue)  High VDD for “fast” logic  Low VDD for “slow” logic  “Level converters” needed between blocks

7. ECE 425 Spring 2007Lecture 10 - Comb. Logic7 More Techniques for Saving Power  DCSL - Differential Current Switch Logic

8. ECE 425 Spring 2007Lecture 10 - Comb. Logic8 More Techniques for Saving Power  DCSL Key Ideas  Similar to DCVS, but with extra transistors T9, T11  Cross-coupled inverters act as a sense amp  T9, T11 disconnect pull down networks  DCSL Operation  CLK low - OUT, OUT’ precharged  CLK high, some inputs high - T9, T10, T11 on  One output drops faster than the other  Cross-coupled inverters reinforce change  Either T9 or T11 cuts off, disconnecting PDN of “high” output Dinesh Somasekhar & Kaushik Roy, "Differential Current Switch Logic: A Low Power DCVS Logic Family", European Conference on Solid State Circuits, September 1995

9. ECE 425 Spring 2007Lecture 10 - Comb. Logic9 More Techniques for Saving Power  Dealing with leakage currents (p. 158)  Multiple-Threshold CMOS (MTCMOS) - Fig 3-37  Variable-Threshold CMOS (VTCMOS) - Fig 3-38 (electrically modify V t by controlling well bias) MTCMOS Inverter High V t Low V t VTCMOS Inverter

10. ECE 425 Spring 2007Lecture 10 - Comb. Logic10 Delay in Long Wires - Lumped RC Model  What is the delay in a long wire?  Lumped RC Model:  Delay time constant (ignoring driving gate)  = R * C = (R s * L / W) * (L * W * C plate ) = r * c * L 2  Problem: Overly Pessimistic R = R s * L / W = r*L (r = R s / W - resistance per unit length ) C = L * W * C plate = c*L (c = W * C plate - capacitance per unit length)

11. ECE 425 Spring 2007Lecture 10 - Comb. Logic11 Delay in Long Wires - Distributed RC Model  Alternative: Break wire into small segments  Approx. Solution - 1st moment of impulse response  Important: delay still grows as square of length

12. ECE 425 Spring 2007Lecture 10 - Comb. Logic12 Delay in Long Wires - Consequences in design  Distributed RC model:  Delay grows as square of L!  Choose wire material that minimizes r, c  Break wire into buffered segments to optimize delay

13. ECE 425 Spring 2007Lecture 10 - Comb. Logic13 Elmore Delay  Consider R-C ladder network with unequal values  First-order time constant at node N is  First-order time constant and node I is

14. ECE 425 Spring 2007Lecture 10 - Comb. Logic14 Elmore Delay Applications  Wire sizing to minimize delay  Delay prediction of complex networks (as long as they take the form of a ladder)

15. ECE 425 Spring 2007Lecture 10 - Comb. Logic15 Elmore Delay Homework Problem  What are the Elmore time constants  1,  2,  3 ?

16. ECE 425 Spring 2007Lecture 10 - Comb. Logic16 Wire Sizing  Recall distributed model of wire: multiple segments note strong impact of R 1, lesser impact of R 2, etc  Idea: Reduce overall delay by tapering segments  Make Segment 1 widest to reduce R1 (increases C1)  Make Segment 2 less wide to reduce R2 (increses C2)  etc.

17. ECE 425 Spring 2007Lecture 10 - Comb. Logic17 Wire Sizing  Ideal Result wire should taper exponentially - see Eq. 3-29, p. 163 [Fis95]:  More pragmatic approach: step-tapered wire [Fis95] J. Fishburn and C. Schevon, “Shaping a distributed-RC line to minimize Elmore delay”, IEEE Trans. on Circuits and Systems-I, December 1995, pp. 1020-1022

18. ECE 425 Spring 2007Lecture 10 - Comb. Logic18 Buffer Insertion  Key Idea: Break long wire up into stages (Sec. 3.7.3)  Equivalent Circuit: Fig. 3-44, p. 167  50% delay of each segment: Eq 3-35  Number of stages for minimum delay: Eq 3-36  Best size and number of stages: Eq 3-38 - 3-39 in out

19. ECE 425 Spring 2007Lecture 10 - Comb. Logic19 Wire Sizing - New Results  Alternative approach [Alpert01]:  Combine buffer insertion and  Untapered wires of (small number of) different widths  Theoretical result: Tapering gives at best 3.5% improvement over this approach  Practical result: tapering generally not worthwhile [Alpert01] “Interconnect Synthesis without wire tapering”, IEEE Trans. CAD, Vol. 20, No. 1, January 2001, pp. 90-104

20. ECE 425 Spring 2007Lecture 10 - Comb. Logic20 Delay in RC-Trees  Many interconnection networks are trees  Extracted RC circuit modeling a gate output  Clock trees

21. ECE 425 Spring 2007Lecture 10 - Comb. Logic21 Delay in RC-Trees: Penfield-Rubenstein Bounds  Key idea: characterize time constants in terms of  Path resistances between nodes  Capacitance values at each node

22. ECE 425 Spring 2007Lecture 10 - Comb. Logic22 Delay in RC-Trees: Penfield-Rubenstein Bounds  Time constants T p, T D o, T R o (eqn. 3-30 - 3-31)  Table 3-2 (p. 165) - bounds for time, voltage

23. ECE 425 Spring 2007Lecture 10 - Comb. Logic23 RC crosstalk  Crosstalk slows down signals---increases settling noise.  Two nets in analysis:  aggressor net causes interference;  victim net is interfered with.

24. ECE 425 Spring 2007Lecture 10 - Comb. Logic24 Aggressors and victims victim net aggressor net

25. ECE 425 Spring 2007Lecture 10 - Comb. Logic25 Wire cross-section  Victim net is surrounded by two aggressors. victimaggressor substrate W S T H  Sakurai’s Estimated Delay: C 21 C 20

26. ECE 425 Spring 2007Lecture 10 - Comb. Logic26 Crosstalk delay vs. wire aspect ratio Increasing aspect ratio (W/T) relative RC delay increased spacing

27. ECE 425 Spring 2007Lecture 10 - Comb. Logic27 Crosstalk delay  There is an optimum wire width for any given wire spacing---at bottom of U curve.  Optimium width increases as spacing between wires increases.

28. ECE 425 Spring 2007Lecture 10 - Comb. Logic28 RLC Delay  Inductance is becoming significant in DSM  Basic analysis: see Section 3.8.1, p. 173  Delay: see Section 3.8.2, p. 174  Buffer insertion: see Section 3.8.3, p. 175

29. ECE 425 Spring 2007Lecture 10 - Comb. Logic29 Coming Up  Combinational Logic Networks (Ch. 4)