1. 1 Matrix Multiplication on SOPC Project instructor: Ina Rivkin Students: Shai Amara Shuki Gulzari Project duration: one semester Semester : Spring 2006 (אביב תשס"ו)

2. 2 Project Goals:   Implementing a Matrix multiplication IP. The IP will multiply N x M sized matrix A with M x L sized matrix B and provide an N x L Result matrix.   Integrating the IP on a system on programmable chip (SOPC).

3. 3 Implementation General Hardware scheme Processor Matrix Multiplication PLB/OPB bridge Uart PLB OPB

4. 4 General Implementation Idea Block diagram Matrix Multiplication unit Memory Logic FSM Clock Address Data Write Enable data address Write enable R0 start signal and sizes of matrices Data out Matrix A Matrix B The result Matrix Mult Accum R1 Finish Bit

5. 5 Actual Implementation Block diagram

6. 6 Finish bit <=1 n, m, l <= sizes Address_A <= i + row*m Address_B <= i*l + col Sel_A <= 1 Sel_B <= 1 Idle start=‘0’ start =‘1’ row <= 0 i <= 0 col <= 0 i <= i +1 Sel_A<=0 Sel_B<=0 i< m-1 WE<=1 Data_out<=data_in Add_out<=row*l+col col<= col+1 i = m-1 row <= row +1 WE <= 0 i<= 0 WE<=0 col < l -1 row < n -1 row = n -1 col = l -1 IP’s FSM